Datasheet 74LVCH32373A Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

74LVCH32373A

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

Product specification
File under Integrated Circuits, IC24

1999 Nov 24

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

FEATURES

• 5 V tolerant inputs/outputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• MULTIBYTE flow-trough standardpin-out architecture

• Low inductance multiple power and ground pins for

minimum noise and ground bounce

• Direct interface with TTL levels

• Bus hold on data inputs

• Typical output ground bounce voltage:

V

<0.8VatVCC= 3.3 V and T

OLP

• Typical output undershoot voltage:
V

>2VatVCC= 3.3 V and T

OHV

• Power off disables outputs, permitting live insertion

• Packaged in plastic fine-pitch ball grid array package.

DESCRIPTION

The 74LVCH32373A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.

amb

amb

=25°C

=25°C

74LVCH32373A

The 74LVCH32373A is a 32-bit transparent D-type latch
featuring separate D-type inputs for each latchand 3-state
outputs for bus oriented applications. One latch enable
(nLE) input and one output enable (nOE) are provided for
each octal. Inputs can be driven from either 3.3 or 5 V
devices.

The74LVCH32373A consists of 4 sectionsof eight D-type
transparent latches with 3-state true outputs. When input
nLE is HIGH, data at the nDn inputs enter the latches. In
this condition the latches are transparent, i.e. a latch
output will change each time its corresponding D-input
changes.

When input nLE is LOW the latches store the information
thatwas present at theD-inputs one set-up time preceding
the HIGH-to-LOW transition of nLE. When input nOE is
LOW, the contents of the eight latches are available at the
outputs. When input nOE is HIGH, the outputs go to the
high-impedance OFF-state. Operation of the nOE input
does not affect the state of the latches.

The 74LVCH32373A bus hold data input circuitseliminate
the need for external pull-up resistors to hold unused
inputs.

The inputs can be driven from either 3.3 or 5 V devices.
In 3-state operation, outputs can handle 5 V. These
features allow the use of these devices in a mixed

3.3 or 5 V environment.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤2.5 ns.

amb

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

C

I

C

PD

propagation delay

nD

to nQ

n

nLE to nQ

n

n

CL= 50 pF; VCC= 3.3 V 3.0 ns

CL= 50 pF; VCC= 3.3 V 3.4 ns
input capacitance 5.0 pF
power dissipation capacitance

VI= GND to VCC; note 1 26 pF
per buffer

Note

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

= input frequency in MHz;

f

i

2

× fi+ Σ (CL× V

CC

2

× fo) where:

CC

fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC= supply voltage in Volts;
Σ (CL× V

2

× fo) = sum of the outputs.

CC

1999 Nov 24 2

Philips Semiconductors Product specification

32-bit transparent D-type latch with

74LVCH32373A

5 V tolerant inputs/outputs; 3-state

FUNCTION TABLE

See note 1.

OPERATING MODE

Enable and read register
(transparent mode)

Latch and read register L L l L L

Latch register and disable
outputs

Note

1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.

OE nLE nD

n

LHLLL
LHHHH

LLhHH
HL l LZ
HLhHZ

INPUTS

n

INTERNAL

LATCHES

OUTPUTS

nQ

n

ORDERING INFORMATION

TYPE NUMBER

74LVCH32373AEC −40 to +85 °C 96 LFBGA96 plastic SOT536-1

PINNING

SYMBOL DESCRIPTION

nD

n

nLE latch enable inputs (active HIGH)
nQ

n

GND ground (0 V)

n

OE output enable inputs (active LOW)

V

CC

TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE

data inputs

data outputs

DC supply voltage

PACKAGE

1999 Nov 24 3

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

handbook, full pagewidth

6

1D11D31D51D72D12D32D52D73D13D33D53D74D14D34D54D

5

1D01D21D41D62D02D22D42D63D03D23D43D64D04D24D44D

1LE 2LE 3LEGND GND GND GND 4LEV

4

1OE

3 2OE 3OEGND GND GND GND 4OEV

1Q01Q21Q41Q62Q02Q22Q42Q63Q03Q23Q43Q64Q04Q24Q44Q

2

1Q11Q31Q51Q72Q12Q32Q52Q73Q13Q33Q53Q74Q14Q34Q54Q

1

AHJBDEG TCF KMNRLP

CC

CC

V

CC

V

CC

Fig.1 Pin configuration.

GND GND GND GNDV

GND GND GND GNDV

CC

CC

74LVCH32373A

MNA492

6

7

V

CC

V

CC

7

6

handbook, full pagewidth

1D

1LE

1OE

3D

3LE

3OE

0

0

DQ

LATCH 1

LE LE

to 7 other channels

DQ

LATCH 17

LE LE

to 7 other channels

1Q

3Q

2D

2LE

2OE

4D

4LE

4OE

0

0

0

0

DQ

LATCH 9

LE LE

to 7 other channels

DQ

LATCH 25

LE LE

to 7 other channels

2Q

0

4Q

0

MNA493

Fig.2 Logic symbol.Fig.2 Logic symbol.

1999 Nov 24 4

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

data

input

V

CC

handbook, halfpage

74LVCH32373A

to internal circuit

MNA473

Fig.3 Bus hold circuit.

1999 Nov 24 5

Philips Semiconductors Product specification

32-bit transparent D-type latch with

74LVCH32373A

5 V tolerant inputs/outputs; 3-state

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS

V

CC

DC supply voltage maximum speed performance 2.7 3.6 V

low-voltage applications 1.2 3.6 V

V

I

V

O

DC input voltage 0 5.5 V
DC output voltage HIGH or LOW state 0 V

3-state 0 5.5 V

T

amb

operating ambient temperature see DC and AC characteristics

−40 +85 °C

per device

t

(∆t/∆f) input rise and fall times VCC= 1.2 to 2.7 V 0 20 ns/V

r,tf

V

= 2.7 to 3.6 V 0 10

CC

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground= 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

V

I

I

IK

I

OK

V

O

DC supply voltage −0.5 +6.5 V
DC input voltage note 1 −0.5 +6.5 V
DC input diode current VI<0 −−50 mA
DC output diode current VO>VCCor VO< 0; note 1 −±50 mA
DC output voltage HIGH or LOW state; note 1 −0.5 VCC+ 0.5 V

3-state; note 1 −0.5 +6.5 V

I

O

I

CC,IGND

T

stg

P

D

DC output source or sink current VO=0toV

CC

−±50 mA
DC VCC or GND current −±100 mA
storage temperature −65 +150 °C
power dissipation per package temperaturerange −40 to +85 °C;

− 1000 mW

note 2

LIMITS

MIN. MAX.

CC

UNIT

V

Notes

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. Above 70 °C the value of P

derates linearly with 1.8 mW/K.

D

1999 Nov 24 6

Philips Semiconductors Product specification

32-bit transparent D-type latch with

74LVCH32373A

5 V tolerant inputs/outputs; 3-state

DC CHARACTERISTICS

Over recommended operating conditions; voltages are referenced to GND (ground=0V).

SYMBOL PARAMETER

TEST CONDITIONS T

OTHER VCC(V) MIN. TYP.

V

IH

HIGH-level input voltage 1.2 V

CC

2.7 to 3.6 2.0 −−

VILLOW-level input voltage 1.2 −−GND V

2.7 to 3.6 −−0.8

V

OH

HIGH-level output voltage VI=VIHor V

IL

IO= −12 mA 2.7 VCC− 0.5 −−V
I

=−100 µA 3.0 VCC− 0.2 V

O

I

= −18 mA 3.0 VCC− 0.6 −−

O

I

=−24 mA 3.0 VCC− 0.8 −−

O

V

OL

LOW-level output voltage VI=VIHor V

IL

IO= 12 mA 2.7 −−0.40 V

= 100 µA 3.0 −−0.20

I

O

I

= 24 mA 3.0 −−0.55

O

I

I

input leakage current VI= 5.5 Vor GND;

3.6 −±0.1 ±5 µA

note 2

I

OZ

3-state output OFF-state current VI=VIHor VIL;

3.6 − 0.1 ±5 µA

VO= 5.5 Vor GND
I
I
∆I

off
CC

CC

power off leakage supply current VIor VO= 5.5 V 0.0 − 0.1 ±10 µA
quiescent supply current VI=VCCor GND; IO= 0 3.6 − 0.1 40 µA
additional quiescent supply

VI=VCC− 0.6 V; IO= 0 2.7 to 3.6 − 5 500 µA

current per input pin

I

BHL

bus hold LOW sustaining current VI= 0.8 V;

3.0 75 −−µA

notes 3, 4 and 5
I

BHH

bus hold HIGH sustaining current VI= 2.0 V;

3.0 −75 −−µA

notes 3, 4 and 5
I

BHLO

I

BHHO

bus hold LOW overdrive current notes 3, 4 and 6 3.6 500 −−µA
bus hold HIGH overdrive current notes 3, 4 and 6 3.6 −500 −−µA

−40 to +85°C

amb

(1)

MAX.

−−V

CC

−

UNIT

Notes

1. All typical values are at V

= 3.3 V and T

CC

amb

=25°C.

2. For bus hold parts the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.

3. Valid for data inputs of bus hold parts (LVCH32-A) only.

4. For data inputs only; control inputs do not have a bus hold circuit.

5. The specified sustaining current at the data input holds the input below the specified VI level.

6. The specified overdrive current at the data input forces the data input to the opposite logic input level.

1999 Nov 24 7

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

AC CHARACTERISTICS

GND = 0 V; tr=tf≤2.5 ns; CL= 50 pF; RL= 500 Ω.

SYMBOL PARAMETER

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

W

t

su

t

h

propagation delay
nDnto nQ

n

propagation delay
nLE to nQ

n

3-state output enable time
nOE to nQ

n

3-state output disable time
nOE to nQ

n

nLE pulse width HIGH see Figs 5 and 8 2.7 3.0 −−ns

set-up time nDn to nLE see Figs 6 and 8 2.7 1.7 −−ns

hold time nDn to nLE see Figs 6 and 8 2.7 1.2 −−ns

see Figs 4 and 8 2.7 1.5 − 5.7 ns

see Figs 5 and 8 2.7 1.5 − 5.8 ns

see Figs 7 and 8 2.7 1.5 − 6.5 ns

see Figs 7 and 8 2.7 1.5 − 6.4 ns

74LVCH32373A

TEST CONDITIONS T

WAVEFORMS VCC(V) MIN. TYP.

3.0 to 3.6 1.5 3.0 4.7

3.0 to 3.6 1.5 3.4 4.8

3.0 to 3.6 1.5 3.5 5.5

3.0 to 3.6 1.5 3.9 5.4

3.0 to 3.6 3.0 2.0 −

3.0 to 3.6 +1.7 −0.1 −

3.0 to 3.6 1.2 0.1 −

= −40 to +85 °C

amb

(1)

MAX.

UNIT

Note

1. All typical values are measured at V

= 3.3 V and T

CC

AC WAVEFORMS

GND

V

OH

V

OL

V

I

handbook, halfpage

nDn input

nQn output

VM= 1.5 V at VCC≥ 2.7 V;
VM= 0.5 × VCCat VCC< 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.

amb

V

M

=25°C.

t

PHL

V

M

t

PLH

MNA494

Fig.4 Input (nDn) to output (nQn) propagation delay times.

1999 Nov 24 8

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

GND

V

OH

V

OL

V

I

V

M

t

PHL

handbook, full pagewidth

nLE input

nQn output

VM= 1.5 V at VCC≥ 2.7 V;
VM= 0.5 × VCCat VCC< 2.7 V;
VOL and VOH are typical output voltage drop that occur with the output load.

74LVCH32373A

V

M

t

W

t

PLH

V

M

MNA495

Fig.5 Latch enable inputs (nLE) pulse width and the latch enable input to outputs (nQn) propagation delay times.

GND

GND

V

I

V

M

t

h

t

su

V

I

V

M

t

t

h

su

MNA496

handbook, full pagewidth

nDn input

nLE input

VM= 1.5 V at VCC≥ 2.7 V;
VM= 0.5 × VCCat VCC< 2.7 V.

Fig.6 Set-up and hold times for inputs (nDn) to inputs (nLE).

1999 Nov 24 9

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

GND

V

CC

V

OL

V

OH

GND

V

I

V

M

enabled

handbook, full pagewidth

nOE input

output
LOW-to-OFF
OFF-to-LOW

output
HIGH-to-OFF
OFF-to-HIGH

t

PLZ

t

PHZ

outputs

74LVCH32373A

t

PZL

V

M

V

X

t

PZH

V

Y

V

M

outputs

disabled

outputs
enabled

MNA478

VM= 1.5 V at VCC≥ 2.7 V;
VM= 0.5 × VCCat VCC< 2.7 V;
VX=VOL+ 0.3 V at VCC≥ 2.7 V;
VX=VOL+ 0.1 V at VCC< 2.7 V;

handbook, full pagewidth

TEST S1

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

open
2 × V
GND

CC

VY=VOH− 0.3VatVCC≥ 2.7 V;
VY=VOH− 0.1VatVCC< 2.7 V;
VOLand VOHare typical output voltage drop that occur with the output load.

Fig.7 3-state output enable and disable times.

S1

V

PULSE

GENERATOR

V

V

CC

<2.7 V V

2.7 to 3.6 V 2.7 V

CC

I

R

CC

D.U.T.

T

V

O

C

50 pF

V

I

Definitions for test circuit:
RL= load resistor.
CL= load capacitance including jig and probe capacitance.
RT= termination resistanceshould be equalto theoutputimpedance

of the pulse generator.

Z

o

R

L

500 Ω

R

L

L

500 Ω

2 × V
open

GND

MNA479

CC

Fig.8 Load circuitry for switching times.

1999 Nov 24 10

Philips Semiconductors Product specification

32-bit transparent D-type latch with

74LVCH32373A

5 V tolerant inputs/outputs; 3-state

PACKAGE OUTLINE

LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm

D

ball A1
index area

A

2

E

detail X

A

A

1

SOT536-1

b

e

T
R
P
N

M

L
K

J
H

G

F
E
D
C
B
A

246135

DIMENSIONS (mm are the original dimensions)

A

UNIT

mm

max.

1.5

A

1bA2

0.41

0.31

1.2

0.9

0.51

0.41

5.6

5.4

D

13.6

13.4

∅ w

M

Z

D

Z

E

e

ye

0.1

Z

0.93

0.58

E

0.8

w

0.2v0.15

vA

Z

D

E

0.93

0.58

A

y

X

0 5 10 mm

scale

OUTLINE
VERSION

SOT536-1

IEC JEDEC EIAJ

REFERENCES

1999 Nov 24 11

EUROPEAN

PROJECTION

ISSUE DATE

98-11-25
99-06-03

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

SOLDERING
Introduction to soldering surface mount packages

Thistextgives a very brief insight toacomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board byscreenprinting, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating,soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

74LVCH32373A

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswith leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement andbefore soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

1999 Nov 24 12

Philips Semiconductors Product specification

32-bit transparent D-type latch with

74LVCH32373A

5 V tolerant inputs/outputs; 3-state

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

SOLDERING METHOD

WAVE REFLOW

(2)

(3)(4)
(5)

suitable

suitable
suitable

(1)

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Nov 24 13

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

74LVCH32373A

NOTES

1999 Nov 24 14

Philips Semiconductors Product specification

32-bit transparent D-type latch with
5 V tolerant inputs/outputs; 3-state

74LVCH32373A

NOTES

1999 Nov 24 15

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Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 245004/01/pp16 Date of release: 1999 Nov 24 Document order number: 9397 750 06466