Page 1
INTEGRATED CIRCUITS
74LVC841A
10-bit transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification
IC24 Data Handbook
1998 Jun 17
Page 2
Philips Semiconductors Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Wide supply voltage range of 1.2 V to 3.6 V
•In accordance with the JEDEC standard no. 8-1 A
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Flow-through pin-out architecture
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr =t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
C
I
C
PD
Dn to Qn;
LE to Q
Input capacitance 5.0 pF
Power dissipation capacitance per latch VI = GND to V
NOTE:
is used to determine the dynamic power dissipation (PD in µW)
1C
PD
P
= CPD × V
D
2
× fi (CL × V
CC
fi = input frequency in MHz; CL = output load capacity in pF;
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
2
× V
× fo) = sum o f t h e o u t p u t s .
L
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
CL = 50 pF;
VCC = 3.3 V
n
2
× fo) where:
CC
74L VC841A
DESCRIPTION
The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-State
operation, outputs can handle 5 V . This feature allows the use of
these devices as translators in a mixed 3.3 V/5 V environment. The
74LVC841A is a 10-bit transparent latch featuring separate D-type
inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE
input are common to all internal latches. The 74LVC841A consists of
ten transparent latches with 3-State true outputs. When LE is HIGH,
data at the D
are transparent, i.e., a latch output will change each time its
inputs enters the latches. In this condition the latches
n
corresponding D-input changes. When LE is LOW the latches store
the information that was present at the D-inputs a set-up time
preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the ten latches are available at the outputs.
When OE
Operation of the OE
is HIGH, the outputs go to the high impedance OFF-state.
input does not affect the state of the latches.
4.5
5.0
CC
1
22 pF
)
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
24-Pin Plastic SO –40°C to +125°C 74LVC841A D 74LVC841A D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +125°C 74LVC841A DB 74LVC841A DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +125°C 74LVC841A PW 7LVC841APW DH SOT355-1
PIN CONFIGURATION
1
OE
2
D
0
3
D
1
4
D
2
5
D
3
6
D
4
7
D
5
8
D
6
9
D
7
10
D
8
11
D
9
12
GND
1998 Jun 17 853-2071 19589
24
23
22
21
20
19
18
17
16
15
14
13
SV01723
V
CC
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
LE
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OE Output enable input (active Low)
2, 3, 4, 5, 6, 7, 8,
9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
12 GND Ground (0 V)
13 LE Latch enable input (active HIGH)
24 V
2
D0 to D9Data inputs
Q0 to Q93-state latch outputs
CC
Positive supply voltage
Page 3
Philips Semiconductors Product specification
OPERATING MODES
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
LOGIC SYMBOL (IEEE/IEC)
13
2
3
4
5
6
7
8
9
10
11
LOGIC DIAGRAM
LE
D
D
D
D
D
D
D
D
D
D
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
8
Q
9
OE
1
0
1
2
3
4
5
6
7
8
9
SV01724
23
22
21
20
19
18
17
16
15
14
LOGIC SYMBOL
13
1
2
3
4
5
6
7
8
9
10
11
C1
EN
1D
74LVC841A
23
22
21
20
19
18
17
16
15
14
SV01725
D
0
DQ
LATCH
LE LE
LE
OE
FUNCTION TABLE for register An or B
Enable and read register (transparent mode)
Latch and read register
latch register and disable outputs
D
1
DQ
1
LATCH
LE LE
Q
0
D
2
DQ
2
LATCH
LE LE
Q
1
D
3
DQ
3
LATCH
LE LE
Q
2
D
4
DQ
4
LATCH
LE LE
Q
3
D
5
DQ
5
LATCH
LE LE
Q
4
D
6
DQ
6
LATCH
LE LE
Q
5
DD
7
DDD
7
LATCH
LE LELE LE LELE LE LE
QQ
6
D
8
QQQ
8
LATCH
LE
Q
7
D
9
9
LATCH
10
Q
8
SV01726
n
INPUTS
OE LE D
L
L
L
L
H
H
H
H
↓
↓
X
X
INTERNAL
n
L
H
l
h
l
h
LATCHES
L
H
L
H
L
H
OUTPUTS
Q0 TO Q
Hold L L X NC NC
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
X = don’t care
Z = high impedance OFF-state
NC = no change
Q
9
9
L
H
L
H
Z
Z
1998 Jun 17
3
Page 4
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
mW
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
RECOMMENDED OPERATING CONDITIONS
MIN MAX
CC
V
V
T
amb
tr, t
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS RATING UNIT
V
CC
I
IK
V
I
OK
V
I
O
I
GND
T
stg
P
TOT
NOTES:
1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC input voltage range 0 5.5 V
I
DC output voltage range 0 V
O
Operating free-air temperature range –40 +85 °C
Input rise and fall times
f
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
0
1
DC supply voltage –0.5 to +6.5 V
DC input diode current VIt 0 –50 mA
DC input voltage Note 2 –0.5 to +5.5 V
I
DC output diode current V
DC output voltage Note 2 –0.5 to VCC +0.5 V
O
DC output source or sink current VO = 0 to V
, I
DC VCC or GND current "100 mA
CC
uVCC or VO t 0 "50 mA
O
CC
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
74LVC841A
LIMITS
CC
20
10
"50 mA
V
ns/V
1998 Jun 17
4
Page 5
Philips Semiconductors Product specification
VIHHIGH level In ut voltage
V
VILLOW level In ut voltage
V
VOHHIGH level out ut voltage
V
IIIn ut leakage current
V
6V; V
GND
"0.1"5µA
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5
VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
IO = –18mA VCC*0.6
IL;
IO = –24mA VCC*1.0
IL;
VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V
;
CC
= 3.
= 5.5V or
I
IO = 24mA 0.55
IL;
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
V
LOW level output voltage
OL
p
I
OZ
I
CC
∆I
3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 "5 µA
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current per
CC
input pin
NOTE:
1 All typical values are at V
p
p
p
= 3.3V and T
CC
amb
= 25°C.
74LVC841A
LIMITS
CC
CC
V
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT
t
PHL/tPLH
t
PHL/tPLH
t
PZH/tPZL
t
PHZ/tPLZ
t
w
t
su
t
h
Propagation delay
Dn to Q
n
Propagation delay
LE to Q
n
3-state output enable time
OE to Q
n
3-state output disable time
OE to Q
n
LE pulse width, HIGH Figure 4 2.0 0.7 – 2.0 ns
Set-up time
Dn to LE
Hold time
Dn to LE
NOTE:
1 All typical values are at V
= 3.3V and T
CC
amb
= 25°C.
= –40C to +85C
amb
LIMITS
MIN TYP
1
MAX MIN MAX
Figures 1, 5 1.5 4.5 6.7 1.5 7.5 ns
Figures 2, 5 1.5 4.9 7.6 1.5 8.6 ns
Figures 3, 5 1.5 5.4 7.9 1.5 8.9 ns
Figures 3, 5 1.5 3.8 5.9 1.5 6.9 ns
Figure 4 2.0 0.5 – 2.0 ns
Figure 4 1.0 –0.5 – 1.0 ns
1998 Jun 17
5
Page 6
Philips Semiconductors Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V
= 0.5 V × V
V
M
V
= 1.5 V at VCC = 3.0 V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
= VOL + 0.3 V a t VCC ≥ 2.7 V
V
X
V
= VOL + 0.1 × VCC at VCC < 2.7 V
X
V
= VOH – 0.3 V at V
Y
= VOH – 0.1 ×VCC at VCC < 2.7 V
V
Y
Dn Input
GND
V
OH
Q
Output
n
V
OL
Figure 1. Input (Dn) to output (Qn) propagation delays.
LE INPUT
GND
V
Qn OUTPUT
V
Figure 2. Latch enable input (LE) pulse width, the latch enable
OE INPUT
Q
OUTPUT
n
LOW-to-OFF
OFF-to-LOW
OUTPUT
Q
n
HIGH-to-OFF
OFF-to-HIGH
at VCC < 2.7 V
CC
≥ 2.7 V
CC
V
I
V
M
t
PHL
V
M
V
I
V
M
t
W
t
PHL
OH
V
M
OL
input to output (Q
V
I
V
GND
V
CC
V
OL
V
OH
GND
outputs
enabled
M
t
) propagation delays.
n
PLZ
V
X
t
PHZ
V
Y
outputs
disabled
t
PZL
t
Figure 3. 3-State enable and disable times.
t
PZH
PLH
t
PLH
SV01727
SV01729
V
M
V
M
SV01728
outputs
enabled
74LVC841A
V
I
Dn INPUT
GND
V
I
LE INPUT
GND
Figure 4. Data set-up and hold times for the
Note to Figure 4: The shaded areas indicate when the input is
permitted to change for predictable output performance
TEST CIRCUIT
PULSE
GENERATOR
Figure 5. Load circuitry for switching times.
V
M
t
su
D
input to LE input.
n
V
I
R
T
V
CC
2.7V V
2.7V – 3.6V 2.7V
V
V
D.U.T.
I
CC
t
su
Open
2 x V
GND
S
500Ω
500Ω
1
CC
t
SV01730
1
SY00003
t
h
V
M
CC
V
O
50pF
C
L
Test S
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
h
2 x V
Open
GND
CC
1998 Jun 17
6
Page 7
Philips Semiconductors Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
74LVC841A
1998 Jun 17
7
Page 8
Philips Semiconductors Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
74LVC841A
1998 Jun 17
8
Page 9
Philips Semiconductors Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
74LVC841A
1998 Jun 17
9
Page 10
Philips Semiconductors Product specification
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74LVC841A
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 06-98
Document order number: 9397-750-04522
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