Page 1
INTEGRATED CIRCUITS
74LVC821A
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger
(3-State)
Product specification 1998 Sep 25
Page 2
Philips Semiconductors Product specification
V
V
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•10-bit positive edge-triggered register
•Independent register and 3-State buffer operation
•Flow-through pin-out architecture
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL
t
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD × V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
2. The condition is VI = GND to V
= 25°C; tr = tf ≤ 2.5 ns
amb
PHL/tPLH
f
max
C
I
C
PD
2
× fi (CL × V
CC
2
× V
× fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Q
n
Maximum clock frequency
Input capacitance 5.0 pF
Power dissipation capacitance per
flip-flop
2
× fo) where:
CC
CC
DESCRIPTION
The 74LVC821A is a high performance, low-power, low-voltage
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5.0V devices. In 3-state
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC821A is a10-bit D-type flip-flop featuring separate D-type
inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE
common to all flip-flops. The ten flip-flops will store the state of their
individual D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE
of the ten flip-flops is available at the outputs.
When OE
Operation of the OE
CL = 50 pF;
= 3.3
CC
Notes 1 and 2 26 pF
74L VC821A
) input are
is LOW, the contents
is HIGH, the outputs go to the high impedance OFF-state.
input does not affect the state of the flip-flops.
5.4 ns
150 MHz
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE ORDERING CODE PKG. DWG. #
24-Pin Plastic SO –40°C to +85°C 74LVC821A D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74LVC821A DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC821A PW SOT355-1
1998 Sep 25 853-1970 20088
2
Page 3
Philips Semiconductors Product specification
OPERATING MODES
INTERNAL FLIP-FLOPS
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL NAME AND FUNCTION
1 OE
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
D0 to D9Data inputs
23, 22, 21, 20,
19, 18, 17, 16,
Q0 to Q93-State flip-flop outputs
15, 14
12 GND Ground (0 V)
13 CP
24 V
CC
FUNCTION TABLE
Load and read register L
Load register and disable outputs H
Hold L H or L X NC NC
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z = high impedance OFF-state
↑ = LOW–to–HIGH clock transition
NC= no change
Output enable input
(active LOW)
Clock input (LOW-to-HIGH,
edge-triggered)
Positive supply voltage
OE CP D
INPUTS
↑
L
↑
↑
H
↑
74LVC821A
OUTPUTS
n
l
h
l
h
L
H
L
H
Q0 to Q
L
H
Z
Z
9
PIN CONFIGURATION
1998 Sep 25
OE
D
D
D
D
D
D
D
D
D
D
GND
LOGIC SYMBOL
1
2
0
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10
8
11
9
12
24
23
22
21
20
19
18
17
16
15
14
13
SA00413
V
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q9
CP
CC
0
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
10
11
3
13
CP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
OE
1
0
1
2
3
4
5
6
7
8
9
SA00414
23
22
21
20
19
18
17
16
15
14
Page 4
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
LOGIC SYMBOL (IEEE/IEC)
13
1
2
3
4
5
6
7
8
9
10
11
C1
EN
1D
23
22
21
20
19
18
17
16
15
14
FUNCTIONAL DIAGRAM
2
D
0
3
D
1
4
D
2
5
D
3
6
D
4
7
D
8
D
9
D
10
D
11
D
CP
13
1
OE
FF0 to FF9
5
6
7
8
9
74LVC821A
3–STATE
OUTPUTS
23
Q
0
22
Q
1
21
Q
2
20
Q
3
Q
19
4
18
Q
5
17
Q
6
16
Q
7
15
Q
8
14
Q
9
LOGIC DIAGRAM
D
0
D
CP CP CP CP CP CP CP CP CP CP
FF0
CP
OE
Q
D
8
SA00416
9
Q
SA00417
9
SA00415
D
1
Q
Q
DQ
0
FF1
Q
D
2
1
DQ
FF2
Q
D
3
2
DQ
FF3
Q
D
3
4
DQ
FF4
Q
D
5
4
DQ
FF5
Q
D
6
5
DQ
FF6
D
7
DDDQQQ
Q
6
D
8
FF7 FF8 FF9
Q
7
1998 Sep 25
4
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
O
V
V
mW
10-bit D-type flip-flop with 5-volt tolerant
74LVC821A
inputs/outputs; positive-edge trigger (3-State)
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
CC
V
V
T
amb
tr, t
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
OK
O
I
O
I
, I
GND
T
stg
P
TOT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC Input voltage range 0 5.5 V
I
DC output voltage range; output HIGH or LOW
state
0 V
CC
DC output voltage range; output 3-State 0 5.5
Operating ambient temperature range in free-air –40 +85 °C
Input rise and fall times
f
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
0
20
10
1
PARAMETER CONDITIONS RATING UNIT
DC supply voltage –0.5 to +6.5 V
DC input diode current VI t0 –50 mA
DC input voltage Note 2 –0.5 to +6.5 V
I
DC output diode current V
uVCC or VO t 0
O
"50
DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5
DC output voltage; output 3-State Note 2 –0.5 to 6.5
DC output source or sink current VO = 0 to V
DC VCC or GND current
CC
CC
"50
"100
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
V
ns/V
mA
mA
mA
1998 Sep 25
5
Page 6
Philips Semiconductors Product specification
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
V
IIInput leakage current
V
V
GND
"0.1
"5
A
10-bit D-type flip-flop with 5-volt tolerant
74LVC821A
inputs/outputs; positive-edge trigger (3-State)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
p
p
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC*0.5
p
VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
= –18mA VCC*0.6
IL;IO
= –24mA VCC*0.8
IL;IO
VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40
V
LOW level output voltage
OL
p
I
I
I
CC
∆I
3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1
OZ
Power off leakage supply VCC = 0.0V; V
off
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current
CC
per input pin
VCC = 3.0V; VI = VIH or VIL;IO = 100µA 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
or VO = 5.5V 0.1
I
= 24mA 0.55
IL;IO
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
NOTES:
1. All typical values are at V
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
= 3.3V and T
CC
amb
= 25°C.
CC
CC
"5
"10
V
µ
µA
µA
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
f
max
t
SU
t
W
h
Propagation delay
CP to Q
n
3-State output enable time
OE to Q
n
3-State output disable time
OE
to Q
n
Clock pulse width
HIGH or LOW
Setup time
Dn to CP
Hold time
Dn to CP
Maximum clock pulse frequency Figure 1 150 200 – 150 – MHz
NOTE:
1. Unless otherwise stated, all typical values are at V
= –40°C to +85°C.
amb
Figures 1, 4 1.5 5.4 7.3 1.5 8.5 ns
Figures 2, 4 1.5 5.5 7.6 1.5 8.8 ns
Figures 2, 4 1.5 3.8 6.2 1.5 6.8 ns
Figure 1 3.3 1.7 – 3.3 – ns
Figure 3 1.9 0.6 – 0.9 – ns
Figure 3 1.5 0 – 1.5 – ns
= 3.3V and T
CC
amb
= 25°C.
MIN TYP
LIMITS
1
MAX MIN MAX
1998 Sep 25
6
Page 7
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
V
= VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
X
V
= VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
Y
1/f
max
V
I
V
t
PHL
M
t
w
CP INPUT
Qn OUTPUT
V
GND
V
OL
OH
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency.
V
M
V
M
V
t
M
PLH
V
M
SA00394
74LVC821A
V
I
CP
INPUT
GND
V
I
Dn
INPUT
GND
V
OH
Qn
OUTPUT
V
OL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 3. Data setup and hold times for the Dn input to the CP
V
M
t
su
t
h
V
M
V
M
t
su
t
h
SW00229
input.
V
I
OE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
V
M
t
PLZ
t
outputs
enabled
PHZ
V
X
V
Y
Figure 2. 3-State enable and disable times.
outputs
disabled
TEST CIRCUIT
S
1
2 x V
V
CC
50pF
Open
2 x V
GND
500Ω
500Ω
1
CC
V
PULSE
GENERATOR
t
PZL
V
M
t
PZH
V
M
outputs
enabled
I
V
CC
t 2.7V V
2.7V – 3.6V 2.7V
R
D.U.T.
T
V
I
CC
Figure 4. Load circuitry for switching times.
V
O
C
L
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Test S
SA00412
Open
GND
SY00003
CC
1998 Sep 25
7
Page 8
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
74LVC821A
1998 Sep 25
8
Page 9
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1
74LVC821A
1998 Sep 25
9
Page 10
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
74LVC821A
1998 Sep 25
10
Page 11
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
NOTES
74LVC821A
1998 Sep 25
11
Page 12
Philips Semiconductors Product specification
10-bit D-type flip-flop with 5-volt tolerant
inputs/outputs; positive-edge trigger (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74LVC821A
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 08-98
Document order number: 9397–750–04584
yyyy mmm dd
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