Datasheet 74LVC74APW, 74LVC74ADB, 74LVC74AD Datasheet (Philips)

INTEGRATED CIRCUITS

74LVC74A

Dual D-type flip-flop with set and reset;
positive-edge trigger

Product specification
IC24 Data Handbook

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1998 Jun 17

Philips Semiconductors Product Specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

FEA TURES

•Wide supply voltage range of 1.2 V to 3.6 V

•In accordance with JEDEC standard no. 8-1A.

•Inputs accept voltages up to 5.5 V

•CMOS low power consumption

•Direct interface with TTL levels

•Output drive capability 50  transmission lines @ 85°C

QUICK REFERENCE DATA

GND = 0 V; T

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW)

PD

= CPD × V

P

D

f

= input frequency in MHz; CL = output load capacity in pF;

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

 (C

L

2. The condition is V

= 25°C; tr = tf ≤ 2.5 ns

amb

SYMBOL

t

PHL/tPLH

f

max

C

I

C

PD

2

× fi  (CL × V

CC

2

× V

× fo) = sum of the outputs.

CC

= GND to V

I

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay
nCP to nQ, nQ
nSD to nQ, nQ
nR

to nQ, nQ

D

Maximum clock frequency 250 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per flip-flop Notes 1 and 2 30 pF

CC.

2

× fo) + (V

CC

2

/RL) × duty factor LOW, where:

O

74LVC74A

DESCRIPTION

The 74LVC74A is a high-performance, low-voltage Si-gate CMOS
device and superior to most advanced CMOS compatible TTL
families.

The 74LVC74A is a dual positive edge triggered, D-type flip-flop with
individual data (D) inputs, clock (CP) inputs, set (S
inputs; also complementary Q and Q

outputs.

The set and reset are asynchronous active LOW inputs and operate
independently of the clock input. Information on the data input is
transferred to the Q output on the LOW-to-HIGH transition of the
clock pulse. The D inputs must be stable one set-up time prior to the
LOW-to-HIGH clock transition, for predictable operation.

Schmitt-trigger action in all data inputs makes the circuit highly
tolerant to slower clock rise and fall times.

CL = 50 pF;
VCC = 3.3 V

3.6

3.5

3.5

) and (RD)

D

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

14-Pin Plastic SO –40°C to +85°C 74LVC74A D 74LVC74A D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC74A DB 74LVC74A DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC74A PW 74LVC74APW DH SOT402-1

PIN CONFIGURATION

1R

1

D

1D

2

1CP

3

1S

4

D

1Q

5

1Q

6
78

GND

1998 Jun 17 853-2070 19589

14
13
12
11
10

9

SV00491

V
2R
2D
2CP
2S
2Q
2Q

CC

D

D

LOGIC SYMBOL (IEEE/IEC)

4
3
2
1

10
11

12
13

2

S

C1
1D
R

S

C2
2D
R

5

6

9

8

SV00332

Philips Semiconductors Product Specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

PIN DESCRIPTION

PIN

NUMBER

1, 13 1RD, 2R
2, 12 1D, 2D Data inputs
3, 11 1CP, 2CP

4, 10 1SD, 2S
5, 9 1Q, 2Q True flip-flop outputs

6, 8 1Q, 2Q Complement flip-flop outputs
7 GND Ground (0 V)
14 V

LOGIC SYMBOL

SYMBOL NAME AND FUNCTION

Asynchronous reset-direct input

D

(active LOW)

Clock input (LOW-to-HIGH, edge
triggered)

Asynchronous set-direct input (active

D

LOW)

CC

Positive supply voltage

410

1S

D2SD

S

1CP
2CP

1D
2D

D

DCPQ

R

D

1RD2R

113

FF

Q

D

2

12

3

11

1Q2Q5

1Q
2Q

SV00492

9

5
9

74LVC74A

FUNCTION TABLE

INPUTS OUTPUTS

S

D

L H X X H L

H L X X L H

L L X X H H

S

D

H H ° L L H
H H ° H H L

NOTES:

H = HIGH voltage level
L = LOW voltage level
X = don“t care
° = LOW-to-HIGH CP transition
Q

= state after the next LOW-to-HIGH CP transition

n+1

FUNCTIONAL DIAGRAM

R

D

CP D Q Q

INPUTS OUTPUTS

R

D

CP D Q

4

1S

D

S

D

DQ
CP FF1

Q

R

D

S

D

DQ
CP FF2

Q

R

D

1Q

1Q

2Q

2Q

1D2

3

1CP

1

1R

D

10

2S

D

2D12
2CP11

13

2R

D

n+1

5

6

9

8

Q

n+1

1998 Jun 17

SV00494

3

Philips Semiconductors Product Specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

V

V

mW

Dual D-type flip-flop with set and reset;
positive-edge trigger

LOGIC DIAGRAM (ONE FLIP-FLOP)

C

C

D

C

R

D

S

D

CP

C
C

RECOMMENDED OPERA TING CONDITIONS

DC supply voltage (for max. speed performance) 2.7 3.6

CC

DC supply voltage (for low-voltage applications) 1.2 3.6

T

V

V

amb

tr, t

DC input voltage range 0 5.5 V

I

DC output voltage range 0 V

O

Operating free-air temperature range –40 +85 °C
Input rise and fall times

f

C

C

C

C

C

VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V

74LVC74A

Q

Q

SV00495

LIMITS

MIN MAX

CC

0
0

20
10

V

ns/V

ABSOLUTE MAXIMUM RATINGS

1

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)

SYMBOL PARAMETER CONDITIONS RATING UNIT

I

GND

V

I

V

I

OK

V

I

T

DC supply voltage –0.5 to +6.5 V

CC

DC input diode current VIt 0 –50 mA

IK

DC input voltage Note 2 –0.5 to +5.5 V

I

DC output diode current V
DC output voltage Note 2 –0.5 to VCC +0.5 V

O

DC output source or sink current VO = 0 to V

O

, I

DC VCC or GND current "100 mA

CC

Storage temperature range –65 to +150 °C

stg

uVCC or VO t 0 "50 mA

O

CC

"50 mA

Power dissipation per package

P

TOT

– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jun 17

4

Philips Semiconductors Product Specification

VIHHIGH level Input voltage

V

VILLOW level Input voltage

V

VOHHIGH level output voltage

V

IIInput leakage current

V

V

GND

"0.1

"5µA

t

ns

Dual D-type flip-flop with set and reset;

74LVC74A

positive-edge trigger

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1 MAX

V

LOW level output voltage

OL

p

I

CC

∆I

Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current per

CC

input pin

NOTES:

1. All typical values are at V

p

p

p

= 3.3V and T

CC

amb

= 25°C.

VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5
VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V

IO = –18mA VCC*0.6

IL;

IO = –24mA VCC*1.0

IL;

VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V

;

= 3.6V;

CC

= 5.5V or

I

IO = 24mA 0.55

IL;

VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA

CC

CC

V

AC CHARACTERISTICS

GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; T

SYMBOL PARAMETER WAVEFORM

Propagation delay
nCP to nQ, nQ

t

t

PHL

PLH

Propagation delay

/

nSD to nQ, nQ
Propagation delay

nRD to nQ, nQ
Clock pulse width HIGH or LOW Figure 1 3.3 1.3 – – –
Set or reset pulse width LOW Figure 2 3.3 1.7 – – –
Removal time set or reset Figure 2 1 –3 – – – ns
Set-up time nD to nCP Figure 1 2.0 0.8 – – – ns
Hold time nD to nCP Figure 1 1 –0.7 – – – ns
Maximum clock pulse frequency Figure 1 150 250 – – – MHz

t

f

W

rem

t

su

t

h

max

NOTE:

1. These typical values are at V

= 3.3V and T

CC

amb

= –40C to +85C

amb

= 25°C.

Figures 1, 3 1.5 3.6 5.2 – 6.0 ns

Figures 2, 3 1.5 3.5 5.4 – 6.4 ns

Figures 2, 3 1.5 3.5 5.4 – 6.4 ns

LIMITS

VCC = 3.3V ±0.3V VCC = 2.7V

MIN TYP

1

MAX MIN MAX

UNIT

1998 Jun 17

5

Philips Semiconductors Product Specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

AC WAVEFORMS

VM = 1.5 V at VCC  2.7 V

= 0.5 S VCC at VCC < 2.7 V

V

M

V

and VOH are the typical output voltage drop that occur with the

OL

output load.

V

I

nD INPUT

GND

V

I

nCP INPUT

GND

V

OH

nQ OUTPUT

V

OL

V

OH

nQ OUTPUT

V

OL

NOTE: The shaded areas indicate when the inputis permitted to change for predictable
output performance.

Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,

clock pulse width, nD to nCP set-up times,

the nCP to nD hold times, output transition times

and maximum clock pulse frequency.

V

M

t

h

t

su

1/f

max

V

M

t

W

t

PHL

V

M

V

M

t

PLH

t

h

t

su

t

PLH

t

PHL

SV00489

TEST CIRCUIT

PULSE
GENERATOR

SWITCH POSITION

TEST S

t

PLH/tPHL

Figure 3. Load circuitry for switching times.

V

I

Open

74LVC74A

S

1

500Ω

500Ω

SV00903

2 * V

Open
GND

CC

V

CC

V

O

D.U.T.

R

T

V

1

CC

< 2.7V V

50pF

C

L

V

I

CC

2.7V2.7–3.6V

V

I

nCP INPUT

GND

INPUT

nS

D

GND

INPUT

nR

D

GND

V

OH

nQ OUTPUT

V

OL

V

OH

nQ

OUTPUT

V

OL

V

I

V

M

t

V

I

W

t

PLH

V

M

V

M

t

PHL

t

W

V

M

t

PHL

t

PLH

V

M

t

rem

SV00490

Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)

propagation delays, the set and reset pulse widths

and the nR

D to nCP removal time.

1998 Jun 17

6

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74LVC74A

1998 Jun 17

7

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

74LVC74A

1998 Jun 17

8

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

74LVC74A

1998 Jun 17

9

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset;
positive-edge trigger

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74LVC74A

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 06-96
Document order number: 9397-750-04487

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