INTEGRATED CIRCUITS
74LVC574A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger
(3-State)
Product specification 1998 Jul 29
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when V
CC
= 0V
•8-bit positive edge-triggered register
•Independent register and 3-State buffer operation
•Flow-through pin-out architecture
DESCRIPTION
The 74LVC574A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC574A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE
the outputs. When OE
impedance OFF-state. Operation of the OE
state of the flip-flops.
The ’574A’ is functionally identical to the ’374A’, but the ’374A’ has a
different pin arrangement.
74L VC574A
) input are
is LOW, the contents of the eight flip-flops is available at
is HIGH, the outputs go to the high
input does not affect the
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTE:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
= CPD x V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
2. The condition is V
=25°C; tr = tf 2.5ns
amb
2
CC
2
x V
x fo) = sum of outputs.
L
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Q
n
maximum clock frequency 150 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per
flip-flop
x fi + (CL x V
= GND to V
I
CC
CC
2
x fo) where:
CL = 50pF
V
= 3.3V 4.8
CC
Notes 1 and 2 20 pF
ns
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC574A D 74LVC574A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC574A DB 74LVC574A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC574A PW 7LVC574APW DH SOT360-1
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
NORTH AMERICA PKG. DWG. #
1998 Jul 29 853-1863 19804
2
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10 GND Ground (0V)
11 CP
20 V
PIN CONFIGURATION
D0-D7 Data inputs
Q0-Q7 Data outputs
Clock input (LOW-to-HIGH,
edge-triggered)
Positive supply voltage
CC
1
OE
2
D0
3
D1
4
D2
5
D3
D4
6
D5
7
D6
8
D7
9
GND
10 11
SA00400
20
V
CC
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
CP
LOGIC SYMBOL (IEEE/IEC)
1
C1
11
EN
2
1D
3
4
5
6
7
8
9
FUNCTIONAL DIAGRAM
2
D0
318
D1 Q1
516
D3 Q3
FF!
6
714
912
to
FF8
D5 Q5
D7 Q7
74LVC574A
19
18
17
16
15
14
13
12
SA00402
Q0
Q2D2
3-State
OUTPUTS
Q4D4
Q6D6
19
174
15
138
LOGIC SYMBOL
2
3
4
5
6
7
8
9
1998 Jul 29
CP
11
1
OE
11
CP
D0
D1
D2
D3
D4
D5
D6
D7
OE
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
SA00401
SA00403
3
Philips Semiconductors Product specification
OPERATING MODES
INTERNAL FLIP-FLOPS
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
O
O
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
LOGIC DIAGRAM
D0
D
CP CP CP CP
FF1
CP
OE
FUNCTION TABLE
Load and read register L
Load register and
disable outputs
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition
Z = High impedance OFF-state
° = LOW-to-HIGH clock transition
D1
Q
Q0
D
FF2
D2
QQQ QQQQ
D
FF3
Q1 Q2 Q3 Q4 Q5 Q6 Q7
D3
D
FF4
INPUTS
OE LE D
°
L
H
H
°
°
°
n
l
h
l
h
74LVC574A
D4
D
CP CP CP CP
FF5
D5
D
FF6
D6
D
FF7
OUTPUTS
Q0 to Q
L
H
L
H
D7
D
FF8
SA00404
7
L
H
Z
Z
RECOMMENDED OPERATING CONDITIONS
CC
V
I
V
T
amb
tr, t
f
1998 Jul 29
LIMITS
MIN MAX
DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC Input voltage range 0 5.5 V
DC output voltage range; output HIGH or LOW
state
0 V
CC
DC output voltage range; output 3-State 0 5.5
Operating ambient temperature range in free-air –40 +85 °C
Input rise and fall times
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
0
20
10
ns/V
4
V
Philips Semiconductors Product specification
V
V
mW
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
V
IIInput leakage current
2
V
V
GND
"0.1
"5µA
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
OK
DC supply voltage –0.5 to +6.5 V
DC input diode current VI t0 –50 mA
DC input voltage Note 2 –0.5 to +6.5 V
I
DC output diode current V
DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5
O
DC output voltage; output 3-State Note 2 –0.5 to 6.5
I
GND
I
O
T
stg
DC output source or sink current VO = 0 to V
, I
DC VCC or GND current "100 mA
CC
Storage temperature range –65 to +150 °C
Power dissipation per package
P
TOT
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
PARAMETER CONDITIONS RATING UNIT
1
uVCC or VO t 0 "50 mA
O
CC
74LVC574A
"50 mA
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
p
p
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC*0.5
p
VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
= –18mA VCC*0.6
IL;IO
= –24mA VCC*0.8
IL;IO
VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40
V
LOW level output voltage
OL
p
I
OZ
I
I
CC
∆I
3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1 "10 µA
Power off leakage supply VCC = 0.0V; V
off
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current
CC
per input pin
VCC = 3.0V; VI = VIH or VIL;IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
or VO = 5.5V 0.1 "10 µA
I
= 24mA 0.55
IL;IO
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
NOTES:
1. All typical values are at V
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
= 3.3V and T
CC
amb
= 25°C.
CC
CC
V
1998 Jul 29
5
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT
t
t
t
t
t
t
t
f
PHL
PLH
PZH
PZL
PHZ
PLZ
t
W
SU
t
h
max
Propagation delay
CP to Q
n
3-State output enable time
OE to Q
n
3-State output disable time
OE to Q
n
Clock pulse width HIGH or LOW 1 3.4 1.7 – 3.4 – – ns
Setup time
Dn to CP
Hold time
Dn to CP
Maximum clock pulse frequency 1 100 – 80 – – MHz
NOTE:
1. Unless otherwise stated, all typical values are at V
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
V
= VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
Y
= –40°C to +85°C.
amb
LIMITS
MIN TYP1MAX MIN MAX TYP
1, 4 1.5 4.8 7.0 1.5 8.0 21 ns
2, 4 1.5 4.0 7.5 1.5 8.5 17 ns
2, 4 1.5 3.5 6.0 1.5 6.5 11 ns
3 2.0 0.3 – 2.0 – – ns
3 1.5 –0.2 – 1.5 – – ns
= 3.3V and T
CC
amb
= 25°C.
nOE INPUT
V
GND
I
V
M
74LVC574A
1/f
max
V
I
CP INPUT
Qn OUTPUT
V
GND
V
OL
V
M
t
t
OH
PHL
V
M
w
V
M
V
M
t
PLH
V
M
SA00394
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width, output transition times and the maximum
clock pulse frequency.
V
I
CP
INPUT
GND
V
I
Dn
INPUT
GND
V
OH
Qn
OUTPUT
V
OL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
M
t
su
t
h
V
M
V
M
t
su
t
h
SW00107
Waveform 2. Data setup and hold times for the Dn input to the
CP input.
V
CC
Q
OUTPUT
n
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
Q
OUTPUT
n
HIGH-to-OFF
OFF-to-HIGH
GND
t
PLZ
outputs
enabled
t
PHZ
V
X
V
Y
outputs
disabled
t
Waveform 3. 3-State enable and disable times.
TEST CIRCUIT
V
CC
V
PULSE
GENERATOR
I
R
T
V
CC
t 2.7V V
2.7V – 3.6V 2.7V
V
D.U.T.
I
CC
Waveform 4. Load circuitry for switching times.
V
O
C
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
50pF
L
Test S
PZL
t
PZH
Open
2 x V
GND
S
500Ω
500Ω
1
CC
V
1
M
V
M
outputs
enabled
SW00207
2 x V
Open
GND
SY00003
CC
1998 Jul 29
6
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LVC574A
1998 Jul 29
7
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
74LVC574A
1998 Jul 29
8
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
74LVC574A
1998 Jul 29
9
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74LVC574A
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 08-98
Document order number: 9397-750-04514
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