Page 1
INTEGRATED CIRCUITS
74LVC573A
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Product specification 1998 Jul 29
Page 2
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when V
•Flow-through pin-out architecture
DESCRIPTION
The 74LVC573A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
CC
= 0V
74L VC573A
The 74LVC573A is an octal D-type transparent latch featuring
separate D-type inputs for each latch and 3-State outputs for
bus-oriented applications. A latch enable (LE) input and an output
enable (OE
The ’573A’ consists of eight D-type transparent latches with 3-State
true outputs. When LE is HIGH, data at the D
latches. In this condition, the latches are transparent, i.e. a latch
output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present
at the D-inputs one setup time preceding the HIGH-to-LOW
transition of LE. When OE
are available at the outputs. When OE
high impedance OFF-state. Operation of the OE
affect the state of the latches.
The ’573A’ is functionally identical to the ’373A’, but the ’373A’ has a
different pin arrangement.
) input are common to all internal latches.
inputs enters the
n
is LOW, the contents of the eight latches
is HIGH, the outputs go to the
input does not
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
t
PHL/tPLH
C
I
C
PD
NOTE:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
= CPD x V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
2. The condition is V
CC
2
x V
x fo) = sum of outputs.
CC
Propagation delay
Dn to Q
n;
LE to Q
n
Input capacitance 5.0 pF
Power dissipation capacitance per latch Notes 1 and 2 20 pF
2
x fi + (CL x V
= GND to V
I
CC
CC
2
x fo) where:
CL = 50pF
VCC = 3.3V 4.3
4.6
ns
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC573A D 74LVC573A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC573A DB 74LVC573A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC573A PW 7LVC573APW DH SOT360-1
TEMPERATURE
RANGE
OUTSIDE
NORTH AMERICA
NORTH AMERICA PKG. DWG. #
1998 Jul 29 853-1862 19804
2
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Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10 GND Ground (0V)
11 LE Latch enable input (active-High)
20 V
PIN CONFIGURATION
D0-D7 Data inputs
Q0-Q7 Data outputs
Positive supply voltage
CC
OE
1
2
D0
3
D1
4
D2
5
D3
D4
6
D5
7
D6
8
D7
9
GND
10 11
SA00395
20
V
CC
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
LE
74LVC573A
LOGIC SYMBOL (IEEE/IEC)
11
C1
1
EN1
2
1D
3
4
5
6
7
8
9
FUNCTIONAL DIAGRAM
318
D1 Q1
516
D3 Q3
6
714
D5 Q5
912
D7 Q7
LATCH
1 to 8
19
18
17
16
15
14
13
12
SA00397
3-State
OUTPUTS
192
Q0D0
174
Q2D2
15
Q4D4
138
Q6D6
LOGIC SYMBOL
2
3
4
5
6
7
8
9
1998 Jul 29
LE
11
1
OE
1
OE
D0
D1
D2
D3
D4
D5
D6
D7
LE
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
19
18
17
16
15
14
13
12
SA00396
SA00398
3
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Philips Semiconductors Product specification
OPERATING MODES
INTERNAL LATCHES
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
LOGIC DIAGRAM
D0
D
LATCH
1
LE
LE
LE
OE
FUNCTION TABLE
Enable and read register
(transparent mode)
Latch and read register L
Latch register and
disable outputs
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition
X = Don’t care
Z = High impedance OFF-state
D1
Q
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D
LATCH
2
LE
LE
D2
QQQ QQQQ
D
LATCH
3
LE
LE
D3
D
LATCH
4
LE
LE
INPUTS
OE LE D
L
L
H
H
L
L
H
H
L
L
L
n
L
H
l
h
l
h
D4
D
LATCH
5
LE
74LVC573A
D5
D
LATCH
6
LE
LE
LE
L
H
L
H
L
H
D6
D
LATCH
7
LE
LE
OUTPUTS
Q0 to Q
D7
D
LATCH
8
LE
LE
SA00399
7
L
H
L
H
Z
Z
1998 Jul 29
4
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
O
V
V
mW
Octal D-type transparent latch with 5-volt
74LVC573A
tolerant inputs/outputs (3-State)
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
CC
V
V
T
amb
tr, t
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
O
I
O
I
, I
GND
T
stg
P
TOT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC Input voltage range 0 5.5 V
I
DC output voltage range; output HIGH or LOW
state
0 V
CC
DC output voltage range; output 3-State 0 5.5
Operating ambient temperature range in free-air –40 +85 °C
Input rise and fall times
f
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
0
20
10
1
PARAMETER CONDITIONS RATING UNIT
DC supply voltage –0.5 to +6.5 V
DC input diode current VI 0 –50 mA
DC input voltage Note 2 –0.5 to +6.5 V
DC output diode current V
VCC or VO 0
O
50
DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5
DC output voltage; output 3-State Note 2 –0.5 to 6.5
DC output source or sink current VO = 0 to V
DC VCC or GND current
CC
CC
50
100
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
V
ns/V
mA
mA
mA
1998 Jul 29
5
Page 6
Philips Semiconductors Product specification
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
V
IIInput leakage current
2
V
V
GND
"0.1
"5
A
Octal D-type transparent latch with 5-volt
74LVC573A
tolerant inputs/outputs (3-State)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
p
p
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC*0.5
p
VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
= –18mA VCC*0.6
IL;IO
= –24mA VCC*0.8
IL;IO
VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40
V
LOW level output voltage
OL
p
I
OZ
I
I
CC
∆I
3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1
Power off leakage supply VCC = 0.0V; V
off
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current
CC
per input pin
VCC = 3.0V; VI = VIH or VIL;IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
or VO = 5.5V 0.1
I
= 24mA 0.55
IL;IO
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
NOTES:
1. All typical values are at V
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
= 3.3V and T
CC
amb
= 25°C.
CC
CC
"10
"10
V
µ
µA
µA
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT
t
PHL
t
PLH
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
t
SU
W
t
h
Propagation delay
Dn to Q
n
Propagation delay
LE to Q
n
3-State output enable time
OE
to Q
n
3-State output disable time
OE to Q
n
LE pulse width HIGH 2 3.2 1.6 – 3.2 – – ns
Setup time
Dn to LE
Hold time
Dn to LE
NOTE:
1. Unless otherwise stated, all typical values are at V
= –40°C to +85°C.
amb
LIMITS
MIN TYP1MAX MIN MAX TYP
1, 5 1.5 4.3 6.2 1.5 7.2 19 ns
2, 5 1.5 4.6 6.5 1.5 7.5 21 ns
2, 5 1.5 3.8 7.5 1.5 8.5 17 ns
3, 5 1.5 3.5 6.0 1.5 6.5 15 ns
4 1.7 0.3 – 1.7 – – ns
4 1.4 0.2 – 1.5 – – ns
= 3.3V and T
CC
amb
= 25°C.
1998 Jul 29
6
Page 7
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
V
= VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
X
V
= VOH –0.3V at VCC w 2.7V ; VY = VOH – 0.1 VCC at VCC t 2.7V
Y
V
I
INPUT
GND
V
OH
OUTPUT
V
OL
Waveform 1. Input (Dn) to output (Qn) propagation delays.
LE INPUT
Qn OUTPUT
Waveform 2. Latch enable input (LE) pulse width, the latch
enable input to output (Q
V
I
nOE INPUT
GND
V
CC
Q
OUTPUT
n
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
Q
OUTPUT
n
HIGH-to-OFF
OFF-to-HIGH
GND
Waveform 3. 3-State enable and disable times.
V
V
GND
V
OL
V
M
t
PHL
V
M
I
V
M
t
w
t
OH
PHL
) propagation delays
n
V
M
t
PLZ
t
PHZ
outputs
enabled
V
M
V
X
V
Y
outputs
disabled
t
t
PZL
PLH
t
t
PZH
PLH
SY00041
SA00388
V
M
V
M
outputs
enabled
SW00207
74LVC573A
V
I
Dn
INPUT
GND
V
I
LE
INPUT
GND
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
Waveform 4. Data setup and hold times for the Dn input to the
LE input.
TEST CIRCUIT
PULSE
GENERATOR
SWITCH POSITION
TEST SWITCH
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
DEFINITIONS
RL =Load resistor
C
= Load capacitance includes jig and probe capacitance
L
=T ermination resistance should be equal to Z
R
T
of pulse generators.
Waveform 5. Load circuitry for switching times.
V
M
th
t
SU
V
M
V
CC
V
IN
R
T
D.U.T.
V
OUT
C
L
Test Circuit for 3-State Outputs
V
CC
Open
2<V
CC
t 2.7V
2.7 – 3.6V
GND
t
SU
V
IN
V
CC
2.7V
th
S
1
RL=500 Ω
RL=500 Ω
OUT
SW00073
2<V
CC
Open
GND
SW00047
1998 Jul 29
7
Page 8
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LVC573A
1998 Jul 29
8
Page 9
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
74LVC573A
1998 Jul 29
9
Page 10
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
74LVC573A
1998 Jul 29
10
Page 11
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
NOTES
74LVC573A
1998 Jul 29
11
Page 12
Philips Semiconductors Product specification
Octal D-type transparent latch with 5-volt
tolerant inputs/outputs (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74LVC573A
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 08-98
Document order number: 9397-750-04513
yyyy mmm dd
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