Page 1
INTEGRATED CIRCUITS
74LVC377
Octal D-type flip-flop with data enable;
positive-edge trigger
Product specification
Supersedes data of 1996 Jun 06
IC24 Data Handbook
1998 Jul 29
Page 2
Philips Semiconductors Product specification
f
Maximum clock frequency
230
MHz
Octal D-type flip-flop with data enable;
positive-edge trigger
FEATURES
•Wide supply voltage range of 1.2V to 3.6V
•Conforms to JEDEC standard 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•Output drive capability 50Ω transmission lines @ 85°C
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1C
PD
= CPD V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
= 25°C; tr =tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Qn;
Input capacitance 5.0 pF
Power dissipation
capacitance per flip-flop
2
x fi (CL V
2
fo) where:
CC
74L VC377
DESCRIPTION
The 74LVC377 is a low-voltage Si-gate CMOS device, superior to
most advanced CMOS compatible TTL families.
The 74LVC377 has eight edge-triggered , D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable E
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Qn) of
the flip-flop. The E
input must be stable only one set-up time prior to
the LOW-to-HIGH transition for predictable operation.
CL = 50pF
VCC = 3.3V
VI = GND to V
CC
1
6.0 ns
22 pF
is LOW. The
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic SO –40°C to +85°C 74LVC377 D 74LVC377 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74LVC377 DB 74LVC377 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC377 PW 74LVC377PW DH SOT360-1
PIN CONFIGURATION
1
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3
GND
20E
19
18
17
16
15
14
13
12
1110
SY00058
V
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
CC
PIN DESCRIPTION
PIN
NUMBER
1 E Data enable input (active LOW)
2, 5, 6,
9, 12, 15,
16, 19
3, 4, 7,
8, 13, 14,
17, 18
10 GND Ground (0V)
11 CP
20 V
SYMBOL FUNCTION
Q0 – Q7 Flip-flop outputs
D0 – D7 Data inputs
Clock input (LOW-to-HIGH,
edge-triggered)
CC
Positive power supply
1998 Jul 29
2
Page 3
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
Octal D-type flip-flop with data enable;
positive-edge trigger
LOGIC SYMBOL
11
3
4
7
8
13
14
17
18
FUNCTION TABLE
OPERATING
MODES
Load ‘1’ l h H
Load ‘0’ l l L
hold
(do nothing)
H = HIGH voltage level
h = HIGH voltage level one set-up time
prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time
prior to the LOW-to-HIGH CP transition
= LOW-to-HIGH transition
X = Don’t care
CP E Dn Q
X
CP
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
1
2
5
6
9
12
15
16
19
SY00059
INPUTS OUTPUT
n
h
H
X
X
no change
no change
LOGIC SYMBOL (IEEE/IEC)
CP
E
D0
D1
D2
D3
D4
D5
D6
11
1
3
4
7
8
13
14
17
18
1C2
G1
2D
74LVC377
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7D7
SY00060
RECOMMENDED OPERA TING CONDITIONS
V
CC
V
CC
V
V
I/O
V
T
amb
tr, t
1998 Jul 29
DC supply voltage (for max. speed performance) 2.7 3.6 V
DC supply voltage (for low-voltage applications) 1.2 3.6 V
DC Input voltage range 0 5.5 V
I
DC Input voltage range for I/Os 0 V
DC output voltage range 0 V
O
Operating free-air temperature range –40 +85 °C
Input rise and fall times
f
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
3
LIMITS
MIN MAX
CC
CC
0
0
20
10
V
V
ns/V
Page 4
Philips Semiconductors Product specification
mW
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
IIInput leakage current
V
V
GND
Not for I/O pins
"0.1
"5µA
Octal D-type flip-flop with data enable;
74LVC377
positive-edge trigger
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
I
GND
V
I
V
I
V
V
I
OK
OUT
OUT
T
CC
IK
I/O
stg
DC supply voltage –0.5 to +6.5 V
DC input diode current VI t0 –50 mA
DC input voltage Note 2 –0.5 to +5.5 V
I
DC input voltage range for I/Os –0.5 to VCC +0.5 V
DC output diode current V
DC output voltage Note 2 –0.5 to VCC +0.5 V
DC output source or sink current VO = 0 to V
, I
DC VCC or GND current "100 mA
CC
Storage temperature range –60 to +150 °C
Power dissipation per package
P
TOT
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
PARAMETER CONDITIONS RATING UNIT
1
uVCC or VO t 0 "50 mA
O
CC
"50 mA
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
LOW level output voltage
OL
p
I
IHZ/IILZ
I
OZ
I
CC
∆I
Input current for common I/O pins VCC = 3.6V; VI = VCC or GND "0.1 "15 µA
3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = VCC or GND 0.1 "10 µA
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
CC
NOTES:
1. All typical values are at V
p
p
p
= 3.3V and T
CC
amb
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC*0.5
VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
= –12mA VCC*0.6
IL;IO
= –24mA VCC*1.0
IL;IO
VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL;IO = 100µA 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
= 24mA 0.55
IL;IO
p
= 25°C.
CC
CC
V
V
1998 Jul 29
4
Page 5
Philips Semiconductors Product specification
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
Octal D-type flip-flop with data enable;
74LVC377
positive-edge trigger
AC CHARACTERISTICS
GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT
t
PHL
t
PLH
f
t
W
t
su
t
h
t
su
t
h
max
Propagation delay
CP to Qn
Clock pulse width
HIGH or LOW
Set-up time
E to CP
Hold time
E to CP
Set-up time
Dn to CP
Hold time
Dn to CP
Maximum clock
pulse frequency
NOTE:
1. Unless otherwise stated, all typical values are at V
= –40°C to +85°C.
amb
= 3.3V and T
CC
LIMITS
MIN TYP
1
MAX MIN TYP MAX
1 6.0 10.2 6.6 11.2 ns
1 4 1.0 5 1.6 ns
2 4 2.3 5 2.9 ns
2 0 –2.2 0 –2.8 ns
3 2 1.3 3 1.8 ns
3 0 –1.2 0 –1.6 ns
1 125 100 MHz
= 25°C.
amb
AC WAVEFORMS
VM = 1.5V at VCC 2.7V.
VM = 0.5 VCC at VCC 2.7V.
VOL and VOH are the typical output voltage drop that occur with the output load.
1/f
V
I
CP INPUT
GND
V
Qn OUTPUT
V
OH
OL
V
M
t
PHL
Waveform 1. Clock (CP) to output (Qn) propagation delays the
clock pulse width and the maximum clock pulse frequency.
MAX
t
w
V
M
t
PLH
SW00078
Waveform 2. Data set-up and hold times from the data input
V
CC
E Input
GND
V
CC
Dn Input
GND
V
CC
CP Input
GND
NOTE: The shaded areas indicate when the input is permitted to change
V
M
t
su
STABLE
V
M
t
su
for predictable output performance.
t
h
t
h
V
M
t
su
t
W
(Dn) and from the enable
input (E
) to the clock (CP).
t
h
SY00061
1998 Jul 29
5
Page 6
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
TEST CIRCUIT
S
1
RL = 1k
R
V
S1
2 V
2 V
2 V
L
= 1k
CC
CC
CC
V
PULSE
GENERATOR
l
R
T
Test Circuit for Outputs
SWITCH POSITION
TEST S
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
1
Open
V
S1
GND
V
cc
D.U.T.
V
< 2.7V
2.7–3.6V
≥ 4.5 V
CC
V
O
CL= 50pF
V
I
V
CC
2.7V
V
CC
V
S1
Open
GND
t
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
W
V
M
(t
)
f
(tr)t
V
M
t
W
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitance
L
= Termination resistance should be equal to Z
R
T
pulse generators.
74LVC377
V
90%
10%
I
0V
(tr)
t
TLH
(tf)
THL
V
I
0V
of
OUT
Waveform 3. Load circuitry for switching times.
SY00044
1998 Jul 29
6
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable; positive-edge
trigger
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LVC377
1998 Jul 29
7
Page 8
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable; positive-edge
trigger
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
74LVC377
1998 Jul 29
8
Page 9
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable; positive-edge
trigger
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
74LVC377
1998 Jul 29
9
Page 10
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable; positive-edge
trigger
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
74LVC377
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Philips Semiconductors and Philips Electronics North America Corporation
register eligible circuits under the Semiconductor Chip Protection Act.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04508
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