Page 1
INTEGRATED CIRCUITS
74LVC374A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger
(3-State)
Product specification 1998 Jul 29
Page 2
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
FEA TURES
•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
•Supply voltage range of 2.7V to 3.6V
•Complies with JEDEC standard no. 8-1A
•CMOS low power consumption
•Direct interface with TTL levels
•High impedance when V
CC
= 0V
•8-bit positive edge-triggered register
•Independent register and 3-State buffer operation
DESCRIPTION
The 74LVC374A is a high-performance, low-power, low-voltage,
Si-gate CMOS device, superior to most advanced CMOS
compatible TTL families.
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTE:
is used to determine the dynamic power dissipation (PD in W):
1. C
PD
= CPD x V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
2. The condition is V
=25°C; tr = tf 2.5ns
amb
2
CC
2
x V
x fo) = sum of outputs.
L
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Q
n
maximum clock frequency 150 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per
flip-flop
x fi + (CL x V
= GND to V
I
CC
CC
2
x fo) where:
Inputs can be driven from either 3.3V or 5V devices. In 3-State
operation, outputs can handle 5V. This feature allows the use of
these devices as translators in a mixed 3.3V/5V environment.
The 74LVC374A is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and 3-State outputs for bus-oriented
applications. A clock (CP) and an output enable (OE
common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs
that meet the setup and hold times requirements on the
LOW-to-HIGH CP transition.
When OE
the outputs. When OE
impedance OFF-state. Operation of the OE
state of the flip-flops.
The ’374’ is functionally identical to the ’574’, but the ’574’ has a
different pin arrangement.
CL = 50pF
VCC = 3.3V 4.8
Notes 1 and 2 20 pF
74L VC374A
) input are
is LOW, the contents of the eight flip-flops is available at
is HIGH, the outputs go to the high
input does not affect the
ns
ORDERING INFORMATION
PACKAGES
20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC374A D 74LVC374A D SOT163-1
20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC374A DB 74LVC374A DB SOT339-1
20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC374A PW 7LVC374APW DH SOT360-1
1998 Jul 29 853-1861 19802
TEMPERATURE
RANGE
2
OUTSIDE
NORTH AMERICA
NORTH AMERICA PKG. DWG. #
Page 3
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
PIN CONFIGURATION
V
1
OE
2
Q0
3
D0
4
D1
5
Q1
6
Q2
7
D2
8
D3
9
Q3 Q4
10 11
GND
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8, 13,
14, 17, 18
2, 5, 6, 9, 12,
15, 16, 19
11 CP
10 GND Ground (0V)
20 V
D0-D7 Data inputs
Q0-Q7 3-state flip-flop outputs
CC
20
CC
Q7
19
D7
18
D6
17
Q6
16
Q5
15
D5
14
D4
13
12
CP
SA00389
Clock input (LOW-to-HIGH,
edge-triggered)
Positive supply voltage
LOGIC SYMBOL (IEEE/IEC)
11
1
32
4 5
7 6
89
13 12
14 15
17 16
18 19
C1
EN1
1D
FUNCTIONAL DIAGRAM
45
D1 Q1
89
D3 Q3
13
14 15
D5 Q5
18 19
D7 Q7
FF1
to
FF8
74LVC374A
SA00391
Q0D0
Q2D2
3-State
OUTPUTS
Q4D4
Q6D6
23
67
12
1617
LOGIC SYMBOL
13
14
17
18
1998 Jul 29
CP
11
1
11
CP
OE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
2
5
6
9
12
15
16
19
SA00390
D0
3
D1
4
D2
7
D3
8
D4
D5
D6
D7
OE
SA00392
3
Page 4
Philips Semiconductors Product specification
OPERATING MODES
INTERNAL FLIP-FLOPS
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
LOGIC DIAGRAM
D0
D
CP CP CP CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
CP
OE
D1
Q
Q0
D
D2
QQQ QQQQ
D
Q1 Q2 Q3 Q4 Q5 Q6 Q7
D3
D
74LVC374A
D4
D
CP CP CP CP
D5
D
D6
D
D7
D
SA00393
FUNCTION TABLE
INPUTS
OE LE D
Load and read register L
Load register and
disable outputs
L
H
H
°
°
°
°
H = HIGH voltage level
h = HIGH voltage level one setup time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one setup time prior to the LOW-to-HIGH CP transition
Z = High impedance OFF-state
° = LOW-to-HIGH clock transition
n
l
h
l
h
OUTPUTS
Q0 to Q
7
L
H
L
H
L
H
Z
Z
1998 Jul 29
4
Page 5
Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
O
V
V
mW
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
CC
V
V
T
amb
tr, t
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
O
I
O
I
, I
GND
T
stg
P
TOT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC input voltage range 0 5.5 V
I
DC output voltage range; output HIGH or LOW
state
0 V
DC output voltage range; output 3-State 0 5.5
Operating ambient temperature range in free-air –40 +85 °C
Input rise and fall times
f
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
0
1
PARAMETER CONDITIONS RATING UNIT
DC supply voltage –0.5 to +6.5 V
DC input diode current VI t0 –50 mA
DC input voltage Note 2 –0.5 to +6.5 V
DC output diode current V
uVCC or VO t 0 "50 mA
O
DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5
DC output voltage; output 3-State Note 2 –0.5 to 6.5
DC output source or sink current VO = 0 to V
DC VCC or GND current "100 mA
CC
CC
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
74LVC374A
CC
20
10
"50 mA
V
ns/V
1998 Jul 29
5
Page 6
Philips Semiconductors Product specification
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
V
IIInput leakage current
2
V
V
GND
"0.1
"5µA
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
p
p
p
V
LOW level output voltage
OL
p
I
OZ
I
I
CC
∆I
3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1 "10 µA
Power off leakage supply VCC = 0.0V; V
off
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current
CC
per input pin
NOTES:
1. All typical values are at V
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
= 3.3V and T
CC
amb
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC*0.5
VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
= –18mA VCC*0.6
IL;IO
= –24mA VCC*0.8
IL;IO
VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL;IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
or VO = 5.5V 0.1 "10 µA
I
= 24mA 0.55
IL;IO
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
= 25°C.
74LVC374A
LIMITS
CC
CC
V
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT
t
t
t
t
t
t
t
f
PHL
PLH
PZH
PZL
PHZ
PLZ
t
W
SU
t
h
max
Propagation delay
CP to Q
n
3-State output enable time
OE to Q
n
3-State output disable time
OE to Q
n
Clock pulse width HIGH or LOW 1 3.0 1.5 – 3.0 – – ns
Setup time
Dn to CP
Hold time
D
to CP
n
maximum clock pulse frequency 1 100 – – 80 – – MHz
NOTE:
1. Unless otherwise stated, all typical values are at V
= –40°C to +85°C.
amb
LIMITS
MIN TYP1MAX MIN MAX TYP
1, 4 1.5 4.8 7.0 1.5 8.0 21 ns
2, 4 1.5 4.8 7.5 1.5 8.5 22 ns
2, 4 1.5 4.3 6.0 1.5 7.0 15 ns
3 2.0 0 – 2.0 – – ns
3 1.5 0.6 – 1.5 – – ns
= 3.3V and T
CC
amb
= 25°C.
1998 Jul 29
6
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
AC WAVEFORMS
VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V
1/f
max
V
I
V
t
M
t
PHL
CP INPUT
Qn OUTPUT
V
GND
V
OL
OH
Waveform 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse width, output transition times and the maximum
clock pulse frequency.
V
I
CP
INPUT
GND
V
I
Dn
INPUT
GND
V
OH
Qn
OUTPUT
V
OL
NOTE: The shaded areas indicate when the input is permitted to change
for predictable output performance.
V
M
t
V
Waveform 2. Data setup and hold times for the Dn input to the
w
V
M
su
t
h
M
CP input.
V
M
V
M
t
PLH
V
M
SA00394
t
su
t
h
V
M
SW00107
74LVC374A
V
I
nOE INPUT
GND
V
CC
Q
OUTPUT
n
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
Q
OUTPUT
n
HIGH-to-OFF
OFF-to-HIGH
GND
Waveform 3. 3-State enable and disable times.
TEST CIRCUIT
PULSE
GENERATOR
2.7V – 3.6V 2.7V
Waveform 4. Load circuitry for switching times.
V
M
t
PLZ
outputs
enabled
V
I
V
CC
t 2.7V V
t
PHZ
R
T
V
CC
V
CC
D.U.T.
I
V
X
V
Y
V
O
C
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
outputs
disabled
50pF
L
Test S
PZL
t
PZH
Open
2 x V
GND
S
1
500Ω
500Ω
1
CC
V
M
V
M
SY00003
outputs
enabled
SW00207
2 x V
CC
Open
GND
1998 Jul 29
7
Page 8
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LVC374A
1998 Jul 29
8
Page 9
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
74LVC374A
1998 Jul 29
9
Page 10
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
74LVC374A
1998 Jul 29
10
Page 11
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
NOTES
74LVC374A
1998 Jul 29
11
Page 12
Philips Semiconductors Product specification
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
74LVC374A
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 08-98
Document order number: 9397-750-04507
yyyy mmm dd
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