Datasheet 74LVC373APW, 74LVC373ADB, 74LVC373AD Datasheet (Philips)

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INTEGRATED CIRCUITS

74LVC373A

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

Product specification 1998 Jul 29

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Page 2

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt

74L VC373A

tolerant inputs/outputs (3-State)

FEA TURES

•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

•Supply voltage range of 2.7V to 3.6V

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•Direct interface with TTL levels

•High impedance when V

DESCRIPTION

The 74LVC373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

= 0V

The 74LVC373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus-oriented applications. A latch enable (LE) input and an output enable (OE

The ’373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the D latches. In this condition, the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW, the latches store the information that was present at the D-inputs one setup time preceding the HIGH-to-LOW transition of LE. When OE are available at the outputs. When OE high impedance OFF-state. Operation of the OE affect the state of the latches.

The ’373’ is functionally identical to the ’573’, but the ’573’ has a different pin arrangement.

) input are common to all internal latches.

is LOW, the contents of the eight latches

is HIGH, the outputs go to the

inputs enters the

input does not

PHL/tPLH

NOTE:

is used to determine the dynamic power dissipation (PD in W):

1. C

= CPD x V

= input frequency in MHz; CL = output load capacity in pF;

= output frequency in MHz; VCC = supply voltage in V;

 (C

2. The condition is V

x V

x fo) = sum of outputs.

Propagation delay Dn to Q

LE to Q

Input capacitance 5.0 pF Power dissipation capacitance per latch Notes 1 and 2 20 pF

x fi +  (CL x V

= GND to V

x fo) where:

CL = 50pF VCC = 3.3V 4.2

4.6

ORDERING INFORMATION

PACKAGES

20-Pin Plastic Shrink Small Outline (SO) –40°C to +85°C 74LVC373A D 74LVC373A D SOT163-1 20-Pin Plastic Shrink Small Outline (SSOP) Type II –40°C to +85°C 74LVC373A DB 74LVC373A DB SOT339-1 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I –40°C to +85°C 74LVC373A PW 7LVC373APW DH SOT360-1

TEMPERATURE

RANGE

OUTSIDE

NORTH AMERICA

NORTH AMERICA PKG. DWG. #

1998 Jul 29 853-1860 19802

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

PIN CONFIGURATION

Q3 Q4

10 11

GND

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE Output enable input (active-Low)

3, 4, 7, 8, 13,

14, 17, 18

2, 5, 6, 9, 12,

15, 16, 19

D0-D7 Data inputs

Q0-Q7 Data outputs

11 LE Latch enable input (active-High) 10 GND Ground (0V) 20 V

LOGIC SYMBOL

3 4 7 8 13 14 1817

13 12

SA00383

Positive supply voltage

74LVC373A

LOGIC SYMBOL (IEEE/IEC)

32 4 5 7 6

89 13 12 14 15 17 16 18 19

FUNCTIONAL DIAGRAM

D1 Q1

D3 Q3 13 14 15

D5 Q5

18 19

D7 Q7

11 1

EN C1

LATCH

1 to 8

SA00385

3-State

OUTPUTS

Q0D0

Q2D2

Q4D4

1617

Q6D6

1998 Jul 29

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

SA00387

SA00384

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Philips Semiconductors Product specification

OPERATING MODES

INTERNAL LATCHES

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

LOGIC DIAGRAM

FUNCTION TABLE

Enable and read register

(transparent mode)

Latch and read register L

Latch register and

disable outputs

H = HIGH voltage level h = HIGH voltage level one setup time prior to the HIGH-to-LOW LE transition L = LOW voltage level l = LOW voltage level one setup time prior to the HIGH-to-LOW LE transition X = Don’t care Z = High impedance OFF-state

QQQ QQQQ

Q1 Q2 Q3 Q4 Q5 Q6 Q7

INPUTS

OE LE D

L L

H H

L H

L L

L H

74LVC373A

SA00386

OUTPUTS

Q0 to Q

H H

H Z

1998 Jul 29

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

Octal D-type transparent latch with 5-volt

74LVC373A

tolerant inputs/outputs (3-State)

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

amb

tr, t

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

, I

GND

stg

TOT

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC supply voltage (for max. speed performance) 2.7 3.6 DC supply voltage (for low-voltage applications) 1.2 3.6 DC Input voltage range 0 5.5 V

DC Output voltage range; output HIGH or LOW state

0 V

DC output voltage range; output 3-State 0 5.5 Operating ambient temperature range in free-air –40 +85 °C

Input rise and fall times

VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V

0 0

20 10

PARAMETER CONDITIONS RATING UNIT

DC supply voltage –0.5 to +6.5 V DC input diode current VI 0 –50 mA DC input voltage Note 2 –0.5 to +6.5 V DC output diode current V

VCC or VO  0 50 mA

DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5 DC output voltage; output 3-State Note 2 –0.5 to 6.5 DC output source or sink current VO = 0 to V DC VCC or GND current 100 mA

50 mA

Storage temperature range –65 to +150 °C Power dissipation per package

– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500 – plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500

ns/V

1998 Jul 29

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Philips Semiconductors Product specification

VIHHIGH level Input voltage

VILLOW level Input voltage

VOHHIGH level output voltage

IIInput leakage current

GND

0.1

5µA

Octal D-type transparent latch with 5-volt

74LVC373A

tolerant inputs/outputs (3-State)

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

VCC = 1.2V V VCC = 2.7 to 3.6V 2.0 VCC = 1.2V GND VCC = 2.7 to 3.6V 0.8 VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC0.5

VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC0.2 V VCC = 3.0V; VI = VIH or V VCC = 3.0V; VI = VIH or V

= –18mA VCC0.6

IL;IO

= –24mA VCC0.8

IL;IO

VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40

LOW level output voltage

∆I

3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1 10 µA Power off leakage supply VCC = 0.0V; V

off

Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA Additional quiescent supply current

per input pin

VCC = 3.0V; VI = VIH or VIL;IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or V

;

= 3.6V;

= 5.5V or

or VO = 5.5V 0.1 10 µA

= 24mA 0.55

IL;IO

VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA

NOTES:

1. All typical values are at V

2. The specified overdrive current at the data input forces the data input to the opposite logic input state.

= 3.3V and T

amb

= 25°C.

1998 Jul 29

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt

74LVC373A

tolerant inputs/outputs (3-State)

AC CHARACTERISTICS

GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT

PHL

PLH

PHL

PLH

PZH

PZL

PHZ

PLZ

Propagation delay Dn to Q

Propagation delay LE to Q

3-State output enable time OE to Q

3-State output disable time OE to Q

LE pulse width HIGH 2 3.0 1.5 – 3.0 – – ns Setup time

to LE

Hold time Dn to LE

NOTE:

1. Unless otherwise stated, all typical values are at V

= –40°C to +85°C.

amb

LIMITS

MIN TYP

MAX MIN MAX TYP

1, 5 1.5 4.2 6.8 1.5 7.8 19 ns

2, 5 1.5 4.6 7.2 1.5 8.2 21 ns

3, 5 1.5 4.8 7.7 1.5 8.7 22 ns

3, 5 1.5 4.3 6.1 1.5 7.1 15 ns

4 2.0 0 – 2.0 – – ns

4 1.5 0.3 – 1.5 – – ns

= 3.3V and T

amb

= 25°C.

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V. VOL and VOH are the typical output voltage drop that occur with the output load. V

= VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V

VY = VOH –0.3V at VCC w 2.7V ; VY = VOH – 0.1 VCC at VCC t 2.7V

INPUT

GND V

OUTPUT

Waveform 1. Input (Dn) to output (Qn) propagation delays.

LE INPUT

Qn OUTPUT

Waveform 2. Latch enable input (LE) pulse width, the latch enable input to output (Q

GND

PHL

) propagation delays

PLH

SY00041

PLH

SA00388

nOE INPUT

GND

OUTPUT

LOW-to-OFF OFF-to-LOW

OUTPUT

HIGH-to-OFF OFF-to-HIGH

GND

PLZ

outputs enabled

PHZ

outputs disabled

Waveform 3. 3-State enable and disable times.

PZL

PZH

outputs enabled

SW00207

1998 Jul 29

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

AC WAVEFORMS

with 5-volt tolerant inputs/outputs VM = 1.5V at VCC w 2.7V; VM =

0.5 VCC at VCC t 2.7V.

VOL and VOH are the typical output voltage drop that occur with the output load. VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V VY = VOH –0.3V at VCC w 2.7V ; VY = VOH – 0.1 VCC at VCC t 2.7V

Dn INPUT

GND

LE INPUT

GND

NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.

Waveform 4. Data setup and hold times for the Dn input to the LE input. (The shaded areas indicate when the input is permitted to change for predictable output performance).

SW00073

74LVC373A

TEST CIRCUIT

PULSE

GENERATOR

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

PLH/tPHL

PLZ/tPZL

PHZ/tPZH

Open

2<V

GND

DEFINITIONS

RL =Load resistor C

= Load capacitance includes jig and probe capacitance

=T ermination resistance should be equal to Z

of pulse generators.

Waveform 5. Load circuitry for switching times.

D.U.T.

OUT

t 2.7V

2.7 – 3.6V

2.7V

RL=500 Ω

OUT

2<V

Open GND

SW00047

1998 Jul 29

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74LVC373A

1998 Jul 29

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

74LVC373A

1998 Jul 29

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

74LVC373A

1998 Jul 29

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs (3-State)

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

74LVC373A

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 08-98 Document order number: 9397-750-04506

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