Datasheet 74LVC373A Datasheet (ST)

■ 5V TOLERANTINPUTS

■ HIGH SPEED:t

■ POWER DOWN PROTECTION ON INPUTS

= 6.8ns (MAX.) atVCC=3V

PD

AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|IOH|=IOL= 24mA (MIN) at VCC=3V

■ PCI BUS LEVELS GUARANTEED AT24 mA

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOLTAGE RANGE:

VCC(OPR) = 1.65V to 3.6V (1.2V Data
Retention)

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 373

■ LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);
MM > 200V

DESCRIPTION

The 74LVC373A is a low voltage CMOS OCTAL
D-TYPE LATCH fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for 1.65 to 3.6 V

CC

operations and low power and low noise
applications.

These 8 bit D-Type latch are controlled by a latch
enable input(LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q

PIN CONNECTION AND IEC LOGIC SYMBOLS

74LVC373A

OCTAL D-TYPE LATCH

HIGH PERFORMANCE

TSSOPSOP

ORDER CODES

PACKAGE TUBE T & R

SOP 74LVC373AM 74LVC373AMTR

TSSOP 74LVC373ATTR

outputs will follow the data input precisely or
inversely. When the LE is taken low,the Q outputs
will be latched precisely or inversely at the logic
level of D input data. While the (OE) input is low,
the 8outputs will be in a normal logic state (high or
low logic level) and while highlevel the outputs will
be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.

1/10February 2002

74LVC373A

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION TRUTH TABLE

PIN No SYMBOL NAME AND FUNCTION

1 OE Asynchronous Master

Reset (Active LOW)

2, 5,6, 9, 12,

Q0 to Q7 3-State Outputs

15, 16,19

3, 4,7, 8, 13,

D0 to D7 Data Inputs

14, 17, 18

11 LE Latch Enable Input
10 GND Ground (0V)
20 V

CC

Positive Supply Voltage

OE LE D Q

HXXZ

LLX
LHLL

LHHH

X : Don’t Care
Z :High Impedance

INPUTS OUTPUT

NO

CHANGE

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V
V
V

I

I

OK

I

or I

I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to thedevice may occur. Functional operation under these conditions is
not implied

absolute maximum rating must be observed

1) I

O

< GND

2) V

O

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage (VCC= 0V)

O

DC Output Voltage (High or Low State) (note 1) -0.5 to VCC+ 0.5

O

DC Input Diode Current

IK

DC Output Diode Current (note 2)
DC Output Current

O

DC VCCor Ground Current per Supply Pin

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

-0.5 to +7.0 V

-0.5 to +7.0 V

-0.5 to +7.0 V
V

-50 mA

-50 mA

± 50 mA

± 100 mA

-65 to +150 °C

300 °C

2/10

74LVC373A

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V
V
V

I

OH,IOL

I

OH,IOL

I

OH,IOL

I

OH,IOL

T

dt/dv Input Rise and Fall Time (note 2) 0 to 10 ns/V

1) Truth Table guaranteed: 1.2V to 3.6V
from 0.8V to 2V at VCC= 3.0V

2) V

IN

DC SPECIFICATIONS

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage (VCC= 0V)

O

Output Voltage (High or Low State) 0 to V

O

High or Low Level Output Current (VCC= 3.0 to 3.6V)
High or Low Level Output Current (VCC= 2.7 to 3.0V)
High or Low Level Output Current (VCC= 2.3 to 2.7V)
High or Low Level Output Current (VCC= 1.65 to 2.3V)
Operating Temperature

op

Test Condition Value

1.65 to 3.6 V
0 to 5.5 V
0 to 5.5 V

CC

± 24 mA
± 12 mA

± 8mA
± 4mA

-55 to 125 °C

V

Symbol Parameter

V

V

V

V

I

off

I

OZ

High Level Input

IH

Voltage

Low Level Input

IL

Voltage

High Level Output

OH

Voltage

Low Level Output

OL

Voltage

Input Leakage

I

I

Current
Power Off Leakage

Current
High Impedance

Output Leakage
Current

Quiescent Supply
Current

ICCincr. per Input

CC

∆I

I

CC

V

CC

(V)

1.65 to 1.95

-40 to 85 °C -55 to 125 °C

Min. Max. Min. Max.

0.65V

CC

0.65V

CC

2.3 to 2.7 1.7 1.7

2.7 to 3.6 2 2

1.65 to 1.95

0.35V

CC

0.35V

2.3 to 2.7 0.7 0.7

2.7 to 3.6 0.8 0.8
I

1.65 to 3.6

1.65

2.3

2.7

3.0

3.0

1.65 to 3.6

1.65

2.3

2.7

3.0

3.6

0

3.6 VI=VIHorV

=-100 µAVCC-0.2 VCC-0.2

O

I

=-4 mA

O

I

=-8 mA

O

=-12 mA

I

O

=-18 mA

I

O

=-24 mA

I

O

IO=100 µA

I

=4 mA

O

=8 mA

I

O

=12 mA

I

O

=24 mA

I

O

V

= 0 to 5.5V

I

V

or VO= 5.5V

I

IL

1.2 1.2

1.7 1.7

2.2 2.2

2.4 2.4

2.2 2.2

0.2 0.2

0.45 0.45

0.7 0.7

0.4 0.4

0.55 0.55
± 5 ± 5 µA

10 10 µA

± 10 ± 10 µA

VO= 0 to 5.5V

3.6

2.7 to 3.6

VI=VCCor GND

or VO= 3.6 to

V

I

5.5V

VIH=VCC-0.6V

10 10

± 10 ± 10

500 500 µA

Unit

V

CC

V

V

V

µA

3/10

74LVC373A

DYNAMIC SWITCHING CHARACTERISTICS

Test Condition Value

=25°C

Symbol Parameter

V

OLP

V

OLV

1) Number of output defined as ”n”. Measured with ”n-1” outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is
measured in the LOW state.

Dynamic Low Level Quiet
Output (note 1)

V

CC

(V)

3.3

= 50pF

C

L

=0V,VIH= 3.3V

V

IL

AC ELECTRICAL CHARACTERISTICS

Test Condition Value

T

A

Min. Typ. Max.

0.8

-0.8

Unit

V

Symbol Parameter

t

PLHtPHL

Propagation Delay
Time D to Q

C

R

(Ω)

t

L

s

(ns)

V

(V)

CC

L

(pF)

1.65 to 1.95 30 1000 2.0 TBD TBD

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 1.5 7.8 1.5 9.4

-40 to 85 °C -55 to 125 °C

= t

r

Min. Max. Min. Max.

Unit

ns

3.0 to 3.6 50 500 2.5 1 6.8 1 8.2

t

PLHtPHL

Propagation Delay
Time LE to Q

1.65 to 1.95 30 1000 2.0 TBD TBD

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 1.5 7.8 1.5 9.4

ns

3.0 to 3.6 50 500 2.5 1 6.8 1 8.2

t

PZLtPZH

Output Enable Time 1.65 to 1.95 30 1000 2.0 TBD TBD

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 1 8.7 1 10.4

ns

3.0 to 3.6 50 500 2.5 1 7.7 1 9.2

t

PLZtPHZ

Output Disable Time 1.65 to 1.95 30 1000 2.0 TBD TBD

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 2 7.6 2 9.1

ns

3.0 to 3.6 50 500 2.5 2 7.0 2 8.4

W

LE Pulse Width
HIGH

t

1.65 to 1.95 30 1000 2.0 TBD TBD

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 3.3 3.3

ns

3.0 to 3.6 50 500 2.5 3.3 3.3

t

Setup Time D to LE

s

(HIGH to LOW)

1.65 to 1.95 30 1000 2.0 TBD TDB

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 2 2

ns

3.0 to 3.6 50 500 2.5 2 2

t

Hold Time D to

h

CLOCK, HIGH or
LOW

1.65 to 1.95 30 1000 2.0 TBD TBD

2.3 to 2.7 30 500 2.0 TBD TBD

2.7 50 500 2.5 1.5 1.5

ns

3.0 to 3.6 50 500 2.5 1.5 1.5

t

OSLH

t

OSHL

1) Skew is defined as the absolute value ofthe difference between theactual propagation delay for anytwo outputs of the samedeviceswitch­ing in the same direction, either HIGH or LOW (t

2) Parameter guaranteed by design

Output ToOutput
Skew Time (note1,

2)

2.7 to 3.6 1 1 ns

OSLH

=|t

PLHm-tPLHn

|, t

OSHL

=|t

PHLm-tPHLn

|

4/10

74LVC373A

CAPACITIVE CHARACTERISTICS

Test Condition Value

=25°C

Symbol Parameter

C

C

Input Capacitance

IN

Power Dissipation Capacitance

PD

(note 1)

V

CC

(V)

1.8 fIN= 10MHz 28

3.3 34

1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Referto Test Circuit). Average operating current can beobtained by the followingequation.I

CC(opr)=CPDxVCCxfIN+ICC

TEST CIRCUIT

T

A

Min. Typ. Max.

4pF

Unit

pF2.5 30

/n (percircuit)

RT=Z

of pulse generator (typically 50Ω)

OUT

TEST CIRCUIT AND WAVEFORM SYMBOL VALUE

Symbol

C

L

R

L=R1

V

S

V

IH

V

M

V

OH

V

X

V

Y

t

r=tr

1.65 to 1.95V 2.3 to 2.7V 2.7V 3.0 to 3.6V

30pF 30pF 50pF 50pF

1000Ω 500Ω 500Ω 500Ω

2xV

V

CC

CC

2xV

V

CC

VCC/2 VCC/2 1.5V 1.5V

V

CC

V

CC

VOL+ 0.15V VOL+ 0.15V VOL+ 0.3V VOL+ 0.3V

VOH- 0.15V VOH- 0.15V VOH- 0.3V VOH- 0.3V

<2.0ns <2.0ns <2.5ns <2.5ns

CC

V

CC

6V 7V

2.7V 3.0V

3.0V 3.5V

5/10

74LVC373A

WAVEFORM 1: PROPAGATION DELAY, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)

WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle)

6/10

WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)

74LVC373A

7/10

74LVC373A

SO-20 MECHANICAL DATA

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 2.65 0.104
a1 0.1 0.2 0.004 0.008
a2 2.45 0.096

b 0.35 0.49 0.014 0.019
b1 0.23 0.32 0.009 0.012

C 0.5 0.020

c1 45° (typ.)

D 12.60 13.00 0.496 0.512

E 10.00 10.65 0.393 0.419

e 1.27 0.050
e3 11.43 0.450

F 7.40 7.60 0.291 0.300

L 0.50 1.27 0.020 0.050

M 0.75 0.029

S8°(max.)

mm. inch

8/10

PO13L

74LVC373A

TSSOP20 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0089

D 6.4 6.5 6.6 0.252 0.256 0.260

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0° 8°0° 8°

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

K

c

L

E

D

E1

PIN 1 IDENTIFICATION

1

0087225C

9/10

74LVC373A

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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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