Datasheet 74LVCH16374ADL, 74LVCH16374ADGG, 74LVC16374ADL, 74LVC16374ADGG Datasheet (Philips)

INTEGRATED CIRCUITS

74LVC16374A/74LVCH16374A

16-bit edge triggered D-type flip-flop with
5 Volt tolerant inputs/outputs (3-State)

Product specification
Supersedes data of 1997 Aug 22
IC24 Data Handbook

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1998 Mar 17

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

FEA TURES

•5 volt tolerant inputs/outputs for interfacing with 5V logic

•Wide supply voltage range of 1.2 V to 3.6 V

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•MULTIBYTE

TM

flow-through standard pin-out architecture

•Low inductance multiple power and ground pins for minimum

noise and ground bounce

•Direct interface with TTL levels

•All data inputs have bus hold (74LVCH16374A only)

•High impedance when V

DESCRIPTION

The 74LVC(H)16374A is a 16-bit edge-triggered flip-flop featuring
separate D-type inputs for each flip-flop and 3-State outputs for bus
oriented applications. The 74LVC16374A consists of 2 sections of
eight positive edge-triggered flip-flops. A clock (CP) input and an
output enable (OE
from either 3.3V or 5V devices. In 3-State operation, outputs can
handle 5V. These features allow the use of these devices in a mixed

3.3V/5V environment.
The flip-flops will store the state of their individual D-inputs that meet

the set-up and hold time requirements on the LOW-to-HIGH CP
transition.

When OE

is LOW, the contents of the flip-flops are available at the
outputs. When OE
OFF-state. Operation of the OE
flip-flops.

The 74LVCH16374A bus hold data inputs eliminates the need for
external pull up resistors to hold unused inputs.

) are provided for each octal. Inputs can be driven

is HIGH, the outputs go to the high impedance

= 0

CC

input does not affect the state of the

PIN CONFIGURATION

1OE
1Q0
1Q1

GND

1Q2

1Q3
V
1Q4
1Q5

GND

1Q6
1Q7
2Q0

2Q1

GND

2Q2
2Q3
V
2Q4

2Q5

GND

2Q6
2Q7
2OE

74L VC16374A/

74L VCH16374A

48

1
2
3

4
5

6
7

CC

8

9
10
11
12
13
14
15
16
17
18

CC

19
20
21
22
23
24

SW00074

1CP

47

1D0

46

1D1

45

GND

44

1D2

43

1D3

42

V

CC

41

1D4

40

1D5

39

GND

38

1D6

37

1D7

36

2D0

35

2D1

34

GND

33

2D2

32

2D3

31

V

CC

30

2D4

29

2D5

28

GND

27

2D6

26

2D7

25

2CP

QUICK REFERENCE DA TA

GND = 0V; T

SYMBOL

t

PHL/tPLH

f

MAX

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in W):

1. C

PD

= CPD × V

P

D

= input frequency in MHz; CL = output load capacity in pF;

f

i

f

= output frequency in MHz; VCC = supply voltage in V;

o

 (C

= 25°C; tr = tf ≤ 2.5 ns

amb

Propagation delay
Cp to Qn

Maximum clock frequency 150 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per flip-flop VCC = 3.3V

CC

2

× V

L

× fo) = sum of outputs.

CC

2

× fi +  (CL × V

PARAMETER CONDITIONS TYPICAL UNIT

2

× fo) where:

CC

CL = 50pF
VCC = 3.3V

1

3.8 ns

30 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

48-Pin Plastic SSOP Type III –40°C to +85°C 74LVC16374A DL VC16374A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVC16374A DGG VC16374A DGG SOT362-1
48-Pin Plastic SSOP Type III –40°C to +85°C 74LVCH16374A DL VCH16374A DL SOT370-1
48-Pin Plastic TSSOP Type II –40°C to +85°C 74LVCH16374A DGG VCH16374A DGG SOT362-1

1998 Mar 17 853-2028 19111

2

Philips Semiconductors Product specification

OPERATING MODES

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

PIN DESCRIPTION

PIN NUMBER SYMBOL NAME AND FUNCTION

1 1OE

2, 3, 5, 6, 8, 9,

11, 12

4, 10, 15, 21,

28, 34, 39, 45

7, 18, 31, 42 V

13, 14, 16, 17,

19, 20, 22, 23

1Q0 to 1Q7 3-State flip-flop outputs

GND Ground (0V)

CC

2Q0 to 2Q7 3-State flip-flop outputs

24 2OE

25 2CP Clock input

36, 35, 33, 32,

30, 29, 27, 26

47, 46, 44, 43,

41, 40, 38, 37

2D0 to 2D7 Data inputs

1D0 to 1D7 Data inputs

48 1CP Clock input

Output enable input
(active LOW)

Positive supply voltage

Output enable input
(active LOW)

LOGIC SYMBOL

74LVC16374A/

74LVCH16374A

241

47
46

44
43
41
40
38
37
36
35
33
32
30
29
27
26

1D0
1D1

1D2
1D3
1D4
1D5
1D6
1D7
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7

1OE 2OE

1CP 2CP

1Q0
1Q1

1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7

2
3

5
6
8
9
11
12
13
14
16
17
19
20
22
23

LOGIC DIAGRAM

1D0

1CP

1OE

DQ

CP

FF1

TO 7 OTHER CHANNELS

1Q0

FUNCTION TABLE

INPUTS

nOE nCP nDx

Load and read register

Load register and disable outputs

L
L

H
H

H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition
Z = high impedance OFF-state

 = LOW-to-HIGH CP transition







2D0

2CP

2OE

48 25

DQ

CP

FF9

TO 7 OTHER CHANNELS

SW00076

l

h

l

h

2Q0

INTERNAL

FLIP-FLOPS

L
H

L
H

SW00075

OUTPUTS

Q0 to Q7

L

H
Z

Z

1998 Mar 17

3

Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

V

V

V

V

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

LOGIC SYMBOL (IEEE/IEC)

1

1OE
1CLK
2OE
2CLK

1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
2D0

2D1
2D2
2D3
2D4
2D5
2D6
2D7

48
24
25

47
46
44
43

41
40

38
37

36
35

33
32

30
29

27
26

1EN

C1

2EN

C2

1D

1 ∇

2 ∇2D

2

1Q0

3

1Q1

5

1Q2

6

1Q3

8

1Q4

9

1Q5

11

1Q6

12

1Q7

13

2Q0

14

2Q1

16

2Q2

17

2Q3

19

2Q4

20

2Q5

22

2Q6

23

2Q7

SW00077

BUS HOLD CIRCUIT

Data Input

74LVC16374A/

74LVCH16374A

V

CC

To internal circuit

SW00044

RECOMMENDED OPERATING CONDITIONS

DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC input voltage range 0 5.5 V

I

DC input voltage range; output HIGH or LOW state 0 V

O

DC output voltage range; output 3-State 0 5.5
Operating free-air temperature range –40 +85 °C

Input rise and fall times

f

T

CC

V

amb

tr, t

VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V

LIMITS

MIN MAX

CC

0
0

20
10

ns/V

1998 Mar 17

4

Philips Semiconductors Product specification

V

V

mW

VIHHIGH level Input voltage

V

VILLOW level Input voltage

V

V

V

V

V

I

100µA

V

0.2

V

VOHHIGH level output voltage

V

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

ABSOLUTE MAXIMUM RATINGS

1

74LVC16374A/

74LVCH16374A

In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS RATING UNIT

V

CC

I

IK

V

I

OK

DC supply voltage –0.5 to +6.5 V
DC input diode current VIt 0 –50 mA
DC input voltage Note 2 –0.5 to +6.5 V

I

DC output diode current V

uVCC or VO t 0 "50 mA

O

DC output voltage; output HIGH or LOW state Note 2 –0.5 to VCC +0.5

O

DC output voltage; output 3-State Note 2 –0.5 to 6.5

I

GND

I

O

T

stg

DC output source or sink current VO = 0 to V

, I

DC VCC or GND current "100 mA

CC

CC

"50 mA

Storage temperature range –65 to +150 °C
Power dissipation per package

P

TOT

– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

p

p

VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5

;

= 3.0V;

p

CC

VCC = 3.0V; VI = VIH or V

=

I

VCC = 3.0V; VI = VIH or V

;

or

;

IH

= –

IL

O

IO = –18mA VCC*0.6

IL;

IO = –24mA VCC*0.8

IL;

VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40

V

I

OZ

I

I

CC

∆I

LOW level output voltage

OL

I

Input leakage current VCC = 3.6V; VI = 5.5V or GND

I

3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL;VO = 5.5V or GND 0.1 "5 µA
Power off leakage supply VCC = 0.0V; V

off

Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 20 µA
Additional quiescent supply

CC

current per input pin

VCC = 3.0V; VI = VIH or VIL;IO = 100µA 0.20
VCC = 3.0V; VI = VIH or V

or VO = 5.5V "10 µA

I

= 24mA 0.55

IL;IO

6

VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA

CC

CC

*

"0.1 "5 µA

CC

V

1998 Mar 17

5

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

74LVC16374A/

74LVCH16374A

DC ELECTRICAL CHARACTERISTICS (Continued)

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

I

BHL

I

BHH

I

BHLO

I

BHHO

Bus hold LOW sustaining current VCC = 3.0V; VI = 0.8V
Bus hold HIGH sustaining current VCC = 3.0V; VI = 2.0V
Bus hold LOW overdrive current VCC = 3.6V
Bus hold HIGH overdrive current VCC = 3.6V

2, 3, 5
2, 3, 5

2, 3, 4
2, 3, 4

75 µA
–75 µA
500 µA

–500 µA

NOTES:

1. All typical values are at V

2. Valid for data inputs of bus hold parts (LVCH16-A) only.

= 3.3V and T

CC

amb

= 25°C.

3. For data inputs only, control inputs do not have a bus hold circuit.

4. The specified sustaining current at the data input holds the input below the specified VI level.

5. The specified overdrive current at the data input forces the data input to the opposite logic input state.

6. For bus hold parts, the bus hold circuit is switched off when V

exceeds VCC allowing 5.5V on the input terminal.

i

AC CHARACTERISTICS

GND = 0V; tR = tF = 2.5ns; CL = 50pF; RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT

t

PHL

t

PLH

t

PZH

t

t

PHZ

t

f

PZL

PLZ

t

W

t

su

t

h

max

Propagation delay
CP to Qn

3-State output enable time
OE to Qn

3-State output disable time
OE to Qn

CP pulse width
HIGH or LOW

Set-up time Dn to CP 3 2.0 0.3 – 1.9 – – ns
Hold time Dn to CP 3 1.5 –0.3 – 1.1 – – ns
Maximum clock pulse

frequency

NOTE:

1. All typical values are at V

= 3.3V and T

CC

amb

= –40°C to +85°C.

amb

LIMITS

MIN TYP

1

MAX MIN MAX MAX

1, 4 1.5 3.8 5.4 1.5 6.4 17 ns

2, 4 1.5 3.6 5.6 1.5 6.6 20 ns

2, 4 1.5 3.9 5.5 1.5 6.5 12 ns

1 3.0 1.5 – 3.0 – – ns

1 100 – – 80 – – MHz

= 25°C.

1998 Mar 17

6

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

AC WAVEFORMS

VM = 1.5V at VCC w 2.7V; VM = 0.5 VCC at VCC t 2.7V.
VOL and VOH are the typical output voltage drop that occur with the
output load.
VX = VOL + 0.3V at VCC w 2.7V; VX = VOL + 0.1 VCC at VCC t 2.7V
VY = VOH –0.3V at VCC w 2.7V; VY = VOH – 0.1 VCC at VCC t 2.7V

1/f

V

I

CP INPUT

GND

V

OH

Qn OUTPUT

V

OL

V

M

t

PHL

Waveform 1. Clock (CP) to output (Qn) propagation delays, the

clock pulse width and the maximum clock pulse frequency

V

I

OE INPUT

GND

V

M

MAX

t

w

V

M

t

PLH

V

SW00078

M

Waveform 3. Data set-up and hold times for the Dn input to the

74LVC16374A/

74LVCH16374A

V

I

CP
INPUT

GND

V

I

Dn
INPUT

GND

V

OH

Qn
OUTPUT

V

OL

NOTE: The shaded areas indicate when the input is permitted to change

V

M

t

su

t

h

V

M

V

M

for predictable output performance.

CP input

t

su

t

h

SW00079

t

V

CC

OUTPUT
LOW-to-OFF
OFF-to-LOW

V

OL

V

OH

OUTPUT
HIGH-to-OFF
OFF-to-HIGH

GND

PLZ

t

outputs
enabled

PHZ

V

X

V

Y

outputs
disabled

Waveform 2. 3-State enable and disable times

t

PZL

V

M

t

PZH

V

M

outputs
enabled

SW00072

TEST CIRCUIT

PULSE

GENERATOR

SWITCH POSITION

TEST SWITCH

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

V

CC

V

IN

D.U.T.

R

T

V

OUT

C

L

Test Circuit for 3-State Outputs

V

CC

Open

2<V

CC

t 2.7V

2.7 – 3.6V

GND

V

IN

V

CC

2.7V

S

1

RL=500 Ω

RL=500 Ω

2<V

Open
GND

CC

DEFINITIONS

RL =Load resistor
C

= Load capacitance includes jig and probe capacitance

L

=Termination resistance should be equal to Z

R

T

of pulse generators.

OUT

SW00047

Waveform 4. Load circuitry for switching times

1998 Mar 17

7

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1

74LVC16374A/

74LVCH16374A

1998 Mar 17

8

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1mm SOT362-1

74LVC16374A/

74LVCH16374A

1998 Mar 17

9

Philips Semiconductors Product specification

16-bit edge triggered D-type flip-flop with 5 Volt
tolerant inputs/outputs (3-State)

DEFINITIONS

74LVC16374A/

74LVCH16374A

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96
Document order number: 9397-750-04534

All rights reserved. Printed in U.S.A.

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