Datasheet 74LVCH162373ADL, 74LVCH162373ADGG, 74LVC162373ADL, 74LVC162373ADGG Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

74LVC162373A; 74LVCH162373A

16-bit D-type transparent latch with
30 Ω series termination resistors;
5 V input/output tolerant; 3-state

Product specification
File under Integrated Circuits, IC24

1999 Aug 05

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

FEATURES

• ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V

• 5 V tolerant input/output for
interfacing with 5 V logic

• Wide supply voltage range of

1.2 to 3.6 V

• Complies with JEDEC standard
no. 8-1A

• CMOS low power consumption

• MULTIBYTE flow-through

standard pin-out architecture

• Lowinductancemultiplepowerand
ground pins for minimum noise and
ground bounce

• Direct interface with TTL levels

• All data inputs have bus hold

(74LVCH162373A only)

• High impedance when VCC=0

• Power off disables outputs,

permitting live insertion.

DESCRIPTION

The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate
D-type inputs for each latch and 3-state outputs for bus oriented applications.
One latch enable (LE) input and one output enable (OE) are provide for each
octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,
outputs can handle 5 V. These features allow the use of these devices in a
mixed 3.3 and 5 V environment.

The74LVC(H)162373consistsof2sectionsofeightD-typetransparentlatches
with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the
latches. In this condition the latches are transparent, i.e. a latch output will
change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the
D-inputs a set-up time preceding the HIGH-to-LOW transition of LE.
When OE isLOW, the contents of the eight latches areavailable at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of the OE input does not affect the state off latches.

The74LVCH162373A bus hold data inputs eliminates the need forexternalpull
up resistors to hold unused inputs.

The 74LVC(H)162373A is designed with 30 Ω series termination resistors in
both HIGH and LOW output stages to reduce line noise.

74LVC162373A;

74LVCH162373A

FUNCTION TABLE (per section of eight bits)

See note 1.

OPERATION MODES

Enable and read register
(transparent mode)

Latch and read register

Latch register and disable outputs

Note

1. H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.

OE LE D

LHL L L
LHH H H
LLl L L

LLh H H
HL l L Z
HLh H Z

INPUTS

n

INTERNAL

LATCHES

OUTPUTS

Q0to Q

7

1999 Aug 05 2

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

74LVC162373A;

74LVCH162373A

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf≤2.5 ns.

amb

SYMBOL PARAMETER CONDITIONS TYPICAL UNIT

t

PHL/tPLH

C

I

C

PD

propagation delay CL= 50 pF; VCC= 3.3 V

D

to Q

n

LE to Q

n

n

3.2 ns

3.5 ns
input capacitance 5.0 pF
power dissipation capacitance per

VCC= 3.3 V; note 1 26.0 pF

latch

Note

1. C

is used to determine the dynamic power dissipation (PDin µW).

PD

PD=CPD× V

= input frequency in MHz;

f

i

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fo= output frequency in MHz;
∑ (CL× V

2

× fo) = sum of outputs;

CC

CL= output load capacitance in pF;
VCC= supply voltage in Volts.

ORDERING INFORMATION

PACKAGE

OUTSIDE NORTH

AMERICA

NORTH AMERICA

TEMPERATURE

RANGE

PINS PACKAGE MATERIAL CODE

74LVC162373ADL VC162373A DL −40 to +85 °C 48 SSOP plastic SOT370-1
74LVC162373ADGG VC162373A DGG 48 TSSOP plastic SOT362-1
74LVCH162373ADL VCH162373A DL 48 SSOP plastic SOT370-1
74LVCH162373ADGG VCH162373A DGG 48 TSSOP plastic SOT362-1

PINNING

PIN SYMBOL DESCRIPTION

11
2, 3, 5, 6, 8, 9, 11, 12 1Q

OE output enable input (active LOW)

to 1Q

0

7

data inputs/outputs
4, 10, 15, 21, 28, 34, 39, 45 GND ground (0 V)
7, 18, 31, 42 V
13, 14, 16, 17, 19, 20, 22, 23 2Q
24 2

CC

to 2Q

0

7

OE output enable input (active LOW)

DC supply voltage

data inputs/outputs

25 2LE latch enable input (active HIGH)
36, 35, 33, 32, 30, 29, 27, 26 2D
47, 46, 44, 43, 41, 40, 38, 37 1D

to 2D

0

to 1D

0

7
7

data inputs

data inputs
48 1LE latch enable input (active HIGH)

1999 Aug 05 3

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

handbook, halfpage

1OE

1Q
1Q

GND

1Q
1Q

V

CC

1Q
1Q

GND

1Q
1Q
2Q
2Q

GND

2Q
2Q

V

CC

2Q
2Q

GND

2Q
2Q

2OE

1
2

0

3

1

4
5

2

6

3

7
8

4

9

5

10
11

6

12

7

162373A

13

0

14

1

15
16

2

17

3

18
19

4

20

5

21
22

6

23

7

24

MNA424

1LE

48

1D

47

0

1D

46

1

GND

45

1D

44

2

1D

43

3

V

42

CC

1D

41

4

1D

40

5

GND

39

1D

38

6

1D

37

7

2D

36

0

2D

35

1

GND

34

2D

33

2

2D

32

3

V

31

CC

2D

30

4

2D

29

5

GND

28

2D

27

6

2D

26

7

2LE

25

handbook, halfpage

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

74LVC162373A;

74LVCH162373A

1

24

1OE

2OE

1D

0

1D

1

1D

2

1D

3

1D

4

1D

5

1D

6

1D

7

2D

0

2D

1

2D

2

2D

3

2D

4

2D

5

2D

6

2D

7
1LE 2LE

48 25

1Q
1Q
1Q
1Q
1Q
1Q
1Q
1Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q
2Q

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

2
3
5
6
8

9
11
12
13
14
16
17
19

20

22

23

MNA425

Fig.1 Pin configuration.

1999 Aug 05 4

Fig.2 Logic symbol.

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

handbook, full pagewidth

1D

1LE

1OE

D

0

Q

LATCH

1

LE LE

to 7 other channels

1Q

Fig.3 Logic diagram.

2D

0

0

2LE

2OE

74LVC162373A;

74LVCH162373A

D

Q

LATCH

9

LE LE

to 7 other channels

2Q

MNA426

0

handbook, halfpage

1OE

1LE

2OE

2LE

1D
1D
1D
1D
1D
1D
1D
1D
2D
2D
2D
2D
2D
2D
2D
2D

1

1EN

48

C3

24

2EN

25

C4

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

3D 1

4D 2

MNA427

0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7

2

1Q

0

3

1Q

1

5

1Q

2

6

1Q

3

8

1Q

4

9

1Q

5

11

1Q

6

12

1Q

7

13

2Q

0

14

2Q

1

16

2Q

2

17

2Q

3

19

2Q

4

20

2Q

5

22

2Q

6

23

2Q

7

handbook, halfpage

input

V

CC

to internal circuit

MNA428

Fig.4 IEC logic symbol.

1999 Aug 05 5

Fig.5 Bus hold circuit.

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

74LVC162373A;

74LVCH162373A

RECOMMENDED OPERATING CONDITIONS

LIMITS

SYMBOL PARAMETER CONDITIONS

UNIT

MIN. MAX.

V

CC

DC supply voltage

for max. speed performance 2.7 3.6 V
for low-voltage applications 1.2 3.6 V

V

I

V

O

DC input voltage range 0 5.5 V
DC output voltage range

output HIGH or LOW state 0 V

CC

V

3-state 0 5.5 V

T

amb

operating ambient temperature see DC and AC characteristics per

−40 +85 °C

device

t

, t

r

f

input rise and fall times VCC= 1.2 to 2.7 V 0 20 ns/V

V

= 2.7 to 3.6 V 0 10 ns/V

CC

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CC

I

IK

V

I

I

OK

V

O

DC supply voltage −0.5 +6.5 V
DC input diode current VI<0 −−50 mA
DC input voltage note 1 −0.5 +5.5 V
DC output diode current VO>VCC or VO<0 −±50 mA
DC output voltage

output HIGH or LOW note 1 −0.5 V

+ 0.5 V

CC

output 3-state note 1 −0.5 +6.5 V

I

O

I

, I

CC

T

stg

P

tot

DC output diode current VO=0toV
DC VCC or GND current −±100 mA

GND

CC

−±50 mA

storage temperature −65 +150 °C
power dissipation plastic shrink

mini-pack (SSOP and TSSOP)

above 60 °C derate linearly with

5.5 mW/K

− 500 mW

Note

1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1999 Aug 05 6

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

DC CHARACTERISTICS

Over recommended operating conditions; voltage are referenced to GND (ground=0V).

TEST CONDITIONS T

SYMBOL PARAMETER

V

IH

V

IL

V

OH

V

OL

I

I

I

OZ

HIGH-level input voltage 1.2 V

LOW-level input voltage 1.2 −−GND V

HIGH-level output voltage VI=VIHor VIL; IO= −6 mA 2.7 VCC− 0.5 −−V

LOW-level output voltage VI=VIHor VIL; IO=6mA 2.7 −−0.40 V

input leakage current VI= 5.5 Vor GND; note 2 3.6 −±0.1 ±5 µA
3-state output OFF-state

current
I
I
∆I

off
CC

CC

power off leakage supply VIor VO= 5.5 V 0.0 − 0.1 ±10 µA

quiescent supply current VI=VCCor GND; IO= 0 3.6 − 0.1 20 µA

additional quiescent

supply current per control

pin
I

BHL

bus hold LOW sustaining

current
I

BHH

bushold HIGH sustaining

current
I

BHLO

bus hold LOW overdrive

current
I

BHHO

bus hold HIGH overdrive

current

V

I=VIH

IO= −100 µA
V

I=VIH

V

I=VIH

V

I=VIH

VI=VIHor VIL;
VO= 5.5 Vor GND

VI=VCC− 0.6 V; IO= 0 2.7 to 3.6 − 5 500 µA

VI= 0.8 V; notes 3, 4 and 5 3.0 75 −−µA

VI= 2.0 V; notes 3, 4 and 5 3.0 −75 −−µA

VI= 0.8 V; notes 3, 4 and 6 3.6 500 −−µA

VI= 0.8 V; notes 3, 4 and 6 3.6 −500 −−µA

OTHER VCC (V)

MIN. TYP.

CC

2.7 to 3.6 2.0 −−

2.7 to 3.6 −−0.8

or VIL;

3.0 VCC− 0.2 V

or VIL; IO= −12 mA 3.0 VCC− 0.8 −−

or VIL; IO= 100 µA 3.0 −−0.20
or VIL; IO=12mA 3.0 −−0.55

3.6 − 0.1 ±5 µA

74LVC162373A;

74LVCH162373A

(°C)

amb

−40 to +85

(1)

MAX.

−−V

CC

−

UNIT

Notes

1. All typical values are at VCC= 3.3 V and T

amb

=25°C.

2. For bus hold parts, the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.

3. Valid for data inputs of bus hold parts (LVCH162373-A) only.

4. For data inputs only, control inputs do not have a bus hold circuit.

5. The specified sustaining current at the data input holds the input below the specified VI level.

6. The specified overdrive current at the data input forces the data input to the opposite logic input state.

1999 Aug 05 7

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

AC CHARACTERISTICS

GND = 0 V; tr=tf≤2.5 ns; T

SYMBOL PARAMETER WAVEFORMS

t

PHL/tPLH

propagation delay

nD

to nQ

n

n

nLE to nQ

t

PZH/tPZL

t

PHZ/tPLZ

t

W

t

su

t

h

3-state output enable time

n

OE to nQ

n

3-state output disable time

OE to nQ

n

n

nLE pulse width HIGH see Fig.7 4.0 2.0 − 3 − ns

set-up time nDnto nLE see Fig.8 +2.0 −0.1 − 1.7 − ns

hold time nDnto nLE see Fig.8 1.5 0.1 − 1.2 − ns

Note

1. Typical values at V

CC

= −40 to +85 °C.

amb

n

= 3.3 V and T

= 3.3 V ±0.3 V VCC= 2.7 V

CC

MIN. TYP.

see Figs 6 and 10 1.5 3.3 5.4 1.5 6.4 ns
see Figs 7 and 10 1.5 3.5 5.8 1.5 6.8 ns
see Figs 9 and 10 1.5 4.0 7.3 1.5 8.3 ns

see Figs 9 and 10 1.5 3.4 4.8 1.5 5.8 ns

=25°C.

amb

74LVC162373A;

74LVCH162373A

LIMITS

(1)

MAX. MIN. MAX.

UNITV

1999 Aug 05 8

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

AC WAVEFORMS

GND

V

OH

V

OL

V

I

V

M

t

PHL

V

M

handbook, halfpage

nDn INPUT

nQn OUTPUT

t

PLH

MNA429

74LVC162373A;

74LVCH162373A

handbook, full pagewidth

Fig.6 The input (nDn) to output (nQn) propagation delay.

V

I

nLE INPUT

nQn OUTPUT

GND

V

OH

V

OL

V

t

PHL

M

t

W

V

M

V

t

PLH

M

MNA430

Fig.7 Latch enable input (nLE) pulse width, the latch enable input to output (nQn) propagation delays.

1999 Aug 05 9

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

GND

GND

V

I

V

M

t

h

t

su

V

I

V

M

t

su

handbook, full pagewidth

nDn INPUT

nLE INPUT

74LVC162373A;

74LVCH162373A

t

h

MNA431

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig.8 Data set-up and hold times for the nDn input to the nLE input.

GND

V

CC

V

OL

V

OH

GND

V

I

V

M

t

PLZ

V

X

t

PHZ

V

Y

outputs

enabled

outputs

disabled

handbook, full pagewidth

nOE INPUT

nQn OUTPUT

LOW-to-OFF
OFF-to-LOW

nQn OUTPUT

HIGH-to-OFF
OFF-to-HIGH

t

PZL

t

PZH

V

M

V

M

outputs
enabled

MNA432

Fig.9 3-state enable and disable times.

1999 Aug 05 10

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

handbook, full pagewidth

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

open
2 × V
GND

1

CC

PULSE

GENERATOR

V

CC

<2.7 V V

2.7 - 3.6 V 2.7 V

V

CC

V

I

CC

R

V

D.U.T.

T

I

V

O

C

L

50 pF

Definitions for test circuit:
RL= Load resistor; see Chapter “AC characteristics”.
CL= Load capacitance including jig and probe capacitance

(see Chapter “AC characteristics”).

= Termination resistance should be equal to the output

R

T

impedance Z

S

R

L

500 Ω

R

L

500 Ω

of the pulse generator.

o

1

MNA296

74LVC162373A;

74LVCH162373A

2 × V

CC
open
GND

Fig.10 Load circuitry for switching times.

1999 Aug 05 11

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

PACKAGE OUTLINES

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm

D

c

y

Z

48

25

74LVC162373A;

74LVCH162373A

E

H

E

A

SOT370-1

X

v M

A

pin 1 index

1

e

0 5 10 mm

DIMENSIONS (mm are the original dimensions)

mm

A

max.

2.8

0.4

0.2

2.35

2.20

2

A3b

0.25

0.3

0.2

p

0.22

0.13

UNIT A1A

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

(1)E(1)

cD

16.00

15.75

24

b

p

scale

eHELLpQZywv θ

7.6

0.635 1.4 0.25

7.4

w M

10.4

10.1

Q

A

2

A

1.0

0.6

1

detail X

1.2

1.0

L

p

L

0.18 0.1

(A )

A

3

θ

(1)

0.85

0.40

o

8

o

0

OUTLINE

VERSION

SOT370-1

IEC JEDEC EIAJ

REFERENCES

MO-118AA

1999 Aug 05 12

EUROPEAN

PROJECTION

ISSUE DATE

93-11-02
95-02-04

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm

D

c

y

Z

48 25

H

74LVC162373A;

74LVCH162373A

E

E

A

SOT362-1

X

v M

A

A

2

A

1

pin 1 index

L

p

L

0.50

0.35

detail X

0.08

124

w M

b

e

DIMENSIONS (mm are the original dimensions).

mm

A

max.

1.2

0.15

0.05

1.05

0.85

2

A3b

0.25

0.28

0.17

p

cD

0.2

0.2

0.1

0.1

UNIT A1A

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

p

0

(1)E(2)

12.6

12.4

2.5

scale

eHELLpQZywvθ

6.2

0.5 1 0.25

6.0

8.3

7.9

5 mm

0.8

0.4

Q

(A )

3

A

θ

0.1

0.8

0.4

o

8

o

0

OUTLINE

VERSION

SOT362-1

IEC JEDEC EIAJ

REFERENCES

MO-153ED

1999 Aug 05 13

EUROPEAN

PROJECTION

ISSUE DATE

93-02-03
95-02-10

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

SOLDERING
Introduction to soldering surface mount packages

Thistextgivesaverybriefinsighttoacomplextechnology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
totheprinted-circuitboard by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

74LVC162373A;

74LVCH162373A

1999 Aug 05 14

Philips Semiconductors Product specification

16-bit D-type transparent latch with 30 Ω series
termination resistors; 5 V input/output tolerant; 3-state

Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

BGA, SQFP not suitable suitable
HLQFP, HSQFP, HSOP, SMS not suitable

(3)

PLCC
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

The package footprint must incorporate solder thieves downstream and at the side corners.

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

WAVE REFLOW

(2)

(3)(4)
(5)

SOLDERING METHOD

suitable

suitable
suitable

74LVC162373A;

74LVCH162373A

(1)

.

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1999 Aug 05 15

Philips Semiconductors – a w orldwide compan y

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Middle East: see Italy

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United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
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Uruguay: see South America
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Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

1999

Internet: http://www.semiconductors.philips.com

67

SCA

Printed in The Netherlands 245004/01/pp16 Date of release: 1999 Aug 05 Document order number: 9397750 05974