Datasheet 74LVC161PW, 74LVC161DB, 74LVC161D Datasheet (Philips)

INTEGRATED CIRCUITS

74LVC161

Presettable synchronous 4-bit binary
counter; asynchronous reset

Product specification
Supersedes data of 1996 Aug 23
IC24 Data Handbook

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1998 May 20

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

FEA TURES

•Wide supply voltage range of 1.2 V to 3.6 V

•In accordance with JEDEC standard no. 8–1A

•Inputs accept voltages up to 5.5 V

•CMOS low power consumption

•Direct interface with TTL levels

•Asynchronous reset

•Synchronous counting and loading

•Two count enable inputs for n–bit cascading

•Positive edge–triggered clock

•Output drive capability 50  transmission lines @85C

DESCRIPTION

The 74LVC161 is a high–performance, low–power, low–voltage,
Si–gate CMOS device and superior to most advanced CMOS
compatible TTL families.

The 74LVC161 is a synchronous presettable binary counter which
features an internal look–head carry and can be used for
high–speed counting. Synchronous operation is provided by having
all flip–flops clocked simultaneously on the positive–going edge of
the clock (CP). The outputs (Q
preset to a HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the data at the
data inputs (D
positive–going edge of the clock (provided that the set–up and hold
time requirements for PE are met). Preset takes place regardless of
the levels at count enable inputs (CEP and CET). A low level at the
master reset input (MR) sets all four outputs of the flip–flops
(Q

to Q3) to LOW level regardless of the levels at CP, PE, CET

0

and CEP inputs (thus providing an asynchronous clear function).
The look–ahead carry simplifies serial cascading of the counters.

Both count enable inputs (CEP and CET) must be HIGH to count.
The CET input is fed forward to enable the terminal count output
(TC). The TC output thus enabled will produce a HIGH output pulse
of a duration approximately equal to a HIGH level output of Q
pulse can be used to enable the next cascaded stage. The
maximum clock frequency for the cascaded counters is determined
by the CP to TC propagation delay and CEP to CP set–up time,
according to the following formula:

74L VC161

to Q3) of the counters may be

0

to D3) to be loaded into the counter on the

0

. This

0

_______________________________

f

=

max

tp

(CP to TC) + tSU (CEP to CP)

(max)

1

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

f

MAX

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1. C

PD

P

= CPD x V

D

= input frequency in MHz; CL = output load capacity in pF;

f

i

f

= output frequency in MHz; VCC = supply voltage in V;

o

Σ (C

L

2. The condition is V

= 25°C; TR = TF  2.5ns

amb

Propagation delay
CP to Q
CP to TC
MR to Q
MR to TC
CET to TC

maximum clock frequency 200 MHz
input capacitance 5.0 pF
power dissipation capacitance per gate notes 1 and 2 39 pF

2

x fi +Σ (CL x V

CC

2

x V

x f

CC

= sum of the outputs

o )

= GND to V

1

PARAMETER CONDITIONS TYPICAL UNIT

CL = 50 pF

n

n

2

x f

CC

CC

where:

o )

VCC = 3.3V 4.9

5.7

5.2

5.7

4.5

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

16-Pin Plastic SO –40°C to +85°C 74LVC161 D 74LVC161 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC161 DB 74LVC161 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC161 PW 74LVC161PW DH SOT403-1

ns

1998 May 20 853-1864 19421

2

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

PIN CONFIGURATION

LOGIC SYMBOL

MR

CP

CEP

1
2

D0

3

D1

4

D2

5

D3

6

16

V

CC

TC

15

Q0

14

Q1

13

Q2

12

Q3

11

CET

107

98GND PE

SF00656

15

74LVC161

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 MR

2 CP

3,4,5,6 D0 to D

7 CEP count enable inputs
8 GND ground (0V)

9 PE

10 CET count enable carry input

14,13,12,11 Q0 to Q

15 TC terminal count output
16 V

CC

LOGIC SYMBOL (IEEE/IEC)

asynchronous master
reset (active LOW)

clock input (LOW-to-HIGH,
edge-triggered)

data inputs

3

parallel enable input
(active LOW)

flip-flop outputs

3

positive supply voltage

3

4

5
6
9PE

V

= Pin 16

CC

GND = Pin 8

D

0

D

1

D

2

D

3

CEP

CET

710

TC

CP MR

21

Q

0

Q

1

Q

2

Q

3

14

13

12
11

SY00065

1

9
7
10

2

3

4

5

6

R
M1
G3

G4

C2 /1,3,4+

,2 D

1

CTR4

4 CT=15

14

13

12

11

15

SY00066

1998 May 20

3

Philips Semiconductors Product specification

Parallel load

Presettable synchronous 4-bit binary counter;
asynchronous reset

FUNCTIONAL DIAGRAM

3456

D

D

3

2

TC 15

Q

Q

3

2

PE9

CET

10

7

CEP

2CP

1

MR

D

D

1

0

PARALLEL LOAD
CIRCUITRY

BINARY
COUNTER

Q

Q

1

0

14 13 12 11

74LVC161

FUNCTION TABLE

OPERATING

MODES

MR CP CEP CET PE Dn Qn TC

Reset (clear) L X X X X X L L

H ↑ X X l l L L
H ↑ X X l h H *

Count H ↑ h h h X count *

Hold H X l X h X q

(do nothing) H X X l h X q

NOTES:

* = The TC output is High when CET is High and the counter

is at Terminal Count (HHHH)
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High

clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High

clock transition
q = Lower case letters indicate the state of the referenced

output one setup time prior to the Low-to-High clock

transition
X = Don’t care
↑ = Low-to-High clock transition

INPUTS OUTPUTS

n
n

*

L

STATE DIAGRAM

0 1 2 3

15

14

13

12 11 10 9

SF00664

SY00068

4

5

6

7

8

TYPICAL TIMING SEQUENCE

MR

PE

D0
D1
D2
D3

CP

CEP
CET

Q0
Q1
Q2
Q3

TC

12 13 14 15 0 1 2

RESET PRESET

INHIBITCOUNT

SY00069

Typical timing sequence: reset outputs to zero; preset to binary
twelve; count to thirteen, fourteen, fifteen, zero, one, and two;
inhibit

1998 May 20

4

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

LOGIC DIAGRAM

D0

CET

CEP

D1

74LVC161

D3D2

PE

CP

MR

FF0 FF1 FF2 FF3

DCPQ

R

D

Q

Q0

DCPQ

R

D

DCPQ

Q

Q1

Q

R

D

Q2 Q3

DCPQ

Q

R

D

TC

SY00070

1998 May 20

5

Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

V

V

P

TOT

Presettable synchronous 4-bit binary counter;
asynchronous reset

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

CC

V

V

T

amb

tr, t

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)

SYMBOL PARAMETER CONDITIONS RATING UNIT

V

I

GND

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC supply voltage (for max. speed performance) 2.7 3.6
DC supply voltage (for low-voltage applications) 1.2 3.6
DC input voltage range 0 5.5 V

I

DC output voltage range 0 V

O

Operating free-air temperature range –40 +85 °C
Input rise and fall times

f

VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V

0
0

1

CC

I

IK

V

I

I

OK

V

O

I

O

, I

T

stg

DC supply voltage –0.5 to +6.5 V
DC input diode current VI 0 –50 mA
DC input voltage Note 2 –0.5 to +5.5 V
DC output diode current V

VCC or VO  0 50 mA

O

DC output voltage Note 2 –0.5 to VCC +0.5 V
DC output source or sink current VO = 0 to V
DC VCC or GND current 100 mA

CC

CC

Storage temperature range –65 to +150 °C
Power dissipation per package

– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and

TSSOP)

above +60°C derate linearly with 5.5 mW/K 500

74LVC161

CC

20
10

50 mA

V

ns/V

mW

1998 May 20

6

Philips Semiconductors Product specification

VIHHIGH level Input voltage

V

VILLOW level Input voltage

V

VOHHIGH level output voltage

V

IIInput leakage current

V

V

GND

0.1

5µA

Presettable synchronous 4-bit binary counter;
asynchronous reset

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

V

LOW level output voltage

OL

p

I

CC

∆I

Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current per

CC

input pin

NOTES:

1. All typical values are at V

p

p

p

= 3.3V and T

CC

amb

= 25°C.

VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC0.5
VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V

IO = –12mA VCC0.6

IL;

IO = –24mA VCC1.0

IL;

VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V

;

= 3.6V;

CC

= 5.5V or

I

IO = 24mA 0.55

IL;

VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA

CC

74LVC161

LIMITS

CC

V

1998 May 20

7

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

AC CHARACTERISTICS

GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; RL = 500; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PLH

t

PHL

t

PHL

t

t

t

rem

t

t

t

f

max

W

W

su

su

su

t

h

Propagation delay
CP to Qn

Propagation delay
CP to TC

Propagation delay
CET to TC

Propagation delay
MR

to Qn

Propagation delay
MR to TC

Clock pulse width
HIGH or LOW

Master reset
width LOW

Removal time
MR

to CP

Set-up time
Dn to CP

Set-up time
PE to CP

Set-up time
CEP, CET to CP

Hold time
Dn, PE, CEP, CET to CP

Maximum clock
pulse frequency

NOTE:

1. These typical values are at V

= 3.3V and T

CC

amb

= –40C to +85C

amb

LIMITS

MIN TYP1MAX MIN MAX TYP

1 – 4.9 8.0 – 9.0 24 ns

1 – 5.7 9.5 – 11 28 ns

2 – 4.5 7.8 – 8.8 22 ns

3 – 5.2 9.0 – 10 28 ns

3 – 5.7 10 – 11 20 ns

1 4.0 1.2 – 5.0 – – ns

3 3.0 1.6 – 4.0 – – ns

3 0 –0.3 – 0 – – ns

4 2.5 1.0 – 3.0 – – ns

4 3.0 1.2 – 3.5 – – ns

5 5.0 2.1 – 5.5 – – ns

4, 5 0 –1.7 – 0 – – ns

1 125 200 – 110 – – MHz

= 25°C.

74LVC161

1998 May 20

8

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

AC WAVEFORMS

VM = 1.5 V at VCC  2.7 V

= 0.5 S VCC at VCC < 2.7 V

V

M

V

and VOH are the typical output voltage drop that occur with the

OL

output load.

1/f

MAX

V

I

CP INPUT

GND

V

OH

Qn, TC OUTPUT

V

OL

Waveform 1. Clock (CP) to outputs (Qn, TC) propagation
delays, the clock pulse width and the maximum clock
frequency .

CET INPUT

GND

V

TC OUTPUT

V

Waveform 2. Input (CET) to output (TC) propagation delays.

V

M

t

w

t

PHL

V

M

V

I

V

M

t

PLH

OH

V

OL

M

t

PLH

t

PHL

SY00072

SY00071

74LVC161

V

I

INPUT

PE

GND

V

I

CP INPUT

GND

V

I

D

INPUT

n

GND

The shaded areas indicate when the input is permitted
to change for predictable output performance.

Waveform 4. Setup and hold times for the input (Dn) and
parallel enable input (PE

V

I

CEP, CET
INPUT

GND

V

I

CP INPUT

GND

NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.

Waveform 5. CEP and CET setup and hold times.

TEST CIRCUIT

V

M

t

V

M

V

V

M

t

suth

t

SU

t

h

t

SU

t

h

SU

t

h

t

SU

t

h

M

SC00137

).

t

suth

V

M

V

M

SC00138

V

I

MR INPUT

GND

CP INPUT

GND

V

OH

Qn, TC OUTPUT

V

OL

V

I

V

M

t

t

w

PHL

t

rem

V

M

SY00073

Waveform 3. Master reset (MR) pulse width, the master reset
to output (Q

, TC) propagation delays and the master reset to

n

clock (CP) removal times.

1998 May 20

V

CC

PULSE
GENERATOR

V

I

D.U.T.

R

T

V

O

SWITCH POSITION

TEST S

t

PLH/tPHL

1

Open

V

CC

< 2.7V V

Waveform 6. Load circuitry for switching times.

9

S

1

2 * V

CC

Open
GND

500Ω

50pF

C

L

V

CC

2.7V2.7–3.6V

500Ω

I

SV00903

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74LVC161

1998 May 20

10

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

74LVC161

1998 May 20

11

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

74LVC161

1998 May 20

12

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

NOTES

74LVC161

1998 May 20

13

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter;
asynchronous reset

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.

74LVC161

LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

Philips Semiconductors and Philips Electronics North America Corporation

register eligible circuits under the Semiconductor Chip Protection Act.

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-04496

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