Datasheet 74LVC14 Datasheet (Fairchild)

=

■

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

February 2008

74LCX14 Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Features

5V tolerant inputs

■

2.3V–3.6V V

■

6.5ns t

PD

Power down high impedance inputs and outputs

■

±24mA output drive (V Implements proprietary noise/EMI reduction circuitry

■

Latch-up performance exceeds JEDEC 78 conditions ESD performance:

■

– Human body model > 2000V – Machine model > 200V

■

Leadless DQFN package

specifications provided

CC

max. (V

3.3V), 10µA I

CC

3.0V)

CC

max.

General Description

The LCX14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitterfree output signals. In addition, they have a greater noise margin than conventional inverters.

The LCX14 has hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations.

The inputs tolerate voltages up to 7V allowing the interface of 5V, 3V and 2.5V systems.

The 74LCX14 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.

Ordering Information

Package

Order Number

74LCX14M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LCX14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX14BQX

74LCX14MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Note:

1. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Number Package Description

(1)

MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC

MO-241, 2.5 x 3.0mm

Wide

All packages are lead free per JEDEC: J-STD-020B standard.

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Connection Diagrams

Pin Assignments for SOIC, SOP, and TSSOP

Pad Assignments for DQFN

Logic Symbol

IEEE/IEC

Truth Table

Input Output

AO

L H

H L

(Top View)

Pin Description

Pin Names Description

I

n

O

n

Inputs Outputs

<

>

=

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Symbol Parameter Rating

V

CC

V

O

I

IK

I

OK

I

O

I

CC

I

GND

T

STG

Note:

2. I

Absolute Maximum Rating must be observed.

O

Supply Voltage –0.5V to +7.0V DC Input Voltage –0.5V to +7.0V

I

DC Output Voltage, Output in HIGH or LOW State DC Input Diode Current, V

GND –50mA

I

(2)

–0.5V to V

DC Output Diode Current V

V

GND –50mA

O

V

O

CC

DC Output Source/Sink Current ±50mA DC Supply Current per Supply Pin ±100mA DC Ground Current per Ground Pin ±100mA Storage Temperature –65°C to +150°C

CC

+ 0.5V

+50mA

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Recommended Operating Conditions

(3)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol Parameter Min. Max. Units

V

CC

V

O

/

I

OH

Note:

3. Unused inputs must be held HIGH or LOW. They may not float.

Supply Voltage Operating 2.0 3.6 V

Data Retention 1.5 3.6 Input Voltage 0 5.5 V

I

Output Voltage, HIGH or LOW State 0 V

I

Output Current

OL

V V V

3.0V–3.6V ±24 mA

CC

2.7V–3.0V ±12

CC

2.3V–2.7V ±8

CC

V

DC Electrical Characteristics

Symbol Parameter V

V

I

OFF

I

CC

I

Positive Input Threshold 2.5 0.9 1.7 V

t+

Negative Input Threshold 2.5 0.4 1.1 V

t–

Hysteresis 2.5 0.3 1.0 V

H

HIGH Level Output Voltage 2.3–3.6 I

OH

LOW Level Output Voltage 2.3–3.6 I

OL

I

Input Leakage Current 2.3–3.6 0 ≤ V

I

Power-Off Leakage Current 0 V Quiescent Supply Current 2.3–3.6 V

CC

Increase in I

per Input 2.3–3.6 V

CC

=

T

–40°C to +85°C

A

(V) Conditions

CC

3.0 1.2 2.2

3.0 0.6 1.5

3.0 0.4 1.2

2.3 I

2.7 I

3.0 I

2.3 I

2.7 I

3.0 I

–100µA V

OH

= -8mA 1.8

OH

–12mA 2.2

OH

–18mA 2.4

OH

–24mA 2.2

OH

100µA 0.2 V

OL

= 8mA 0.6

OL

12mA 0.4

OL

16mA 0.4

OL

24mA 0.55

OL

5.5V ±5.0 µA

I

or V

I

3.6V ≤ V

IH

5.5V 10 µA

O

V

or GND 10 µA

CC

5.5V ±10

I

V

– 0.6V 500 µA

CC

– 0.2 V

CC

=

≤

=

≤

∆

=

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

UnitsMin. Max.

AC Electrical Characteristics

T

–40°C to +85°C, R

A

V

Symbol Parameter

t

PHL

t

OSHL

, t , t

Propagation Delay 1.5 6.5 1.5 7.5 1.5 7.8 ns

PLH

Output to Output Skew

OSLH

(4)

= 3.3V ± 0.3V,

CC

CL = 50pF

Min. Max. Min. Max. Min. Max.

1.0 ns

VCC = 2.7V,

CL = 50pF

Note:

4. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t

) or LOW-to-HIGH (t

OSHL

OSLH

).

500 Ω

L

VCC = 2.5V ± 0.2V,

CL = 30pF

Units

Dynamic Switching Characteristics

T

= 25°C

A

Symbol Parameter VCC (V) Conditions

V

OLP

OLV

Quiet Output Dynamic Peak V

Quiet Output Dynamic Valley V

OL

3.3 CL = 50pF, VIH = 3.3V, VIL = 0V 0.8 V

2.5 C

= 30pF, VIH = 2.5V, VIL = 0V 0.6

L

3.3 CL = 50pF, VIH = 3.3V, VIL = 0V –0.8 V

2.5 C

= 30pF, VIH = 2.5V, VIL = 0V –0.6

L

Capacitance

Symbol Parameter Conditions Typical Units

C

OUT

PD

Input Capacitance VCC = Open, VI = 0V or V

IN

Output Capacitance VCC = 3.3V, VI = 0V or V

CC

Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10MHz 25 pF

7pF 8pF

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

UnitTypical

AC Loading and Waveforms (Generic for LCX Family)

Test Switch

t

PLH

t

PZL

t

PZH

, t , t

, t

Open

PHL

6V at VCC = 3.3 ± 0.3V

PLZ

VCC x 2 at VCC = 2.5 ± 0.2V GND

PHZ

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Figure 1. AC Test Circuit (C

includes probe and jig capacitance)

L

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and t

Waveforms

rec

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

3-STATE Output Low Enable and

Disable Times for Logic

Symbol

V

mi

V

mo

V

x

V

y

V

CC

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

1.5V 1.5V V

1.5V 1.5V V VOL + 0.3V VOL + 0.3V VOL + 0.15V VOH – 0.3V VOH – 0.3V VOH – 0.15V

CC

/ 2 / 2

t

rise

and t

fall

Figure 2. Waveforms (Input Characteristics; f = 1MHz, tr = tf = 3ns)

Schematic Diagram (Generic for LCX Family)

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Tape and Reel Specification

Tape Format for DQFN

Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status

BQX Leader (Start End) 125 (Typ.) Empty Sealed

Carrier 3000 Filled Sealed

Tr ailer (Hub End) 75 (Typ.) Empty Sealed

Tape Dimensions inches (millimeters)

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Reel Dimensions inches (millimeters)

Tape Size A B C D N W1 W2

12mm 13.0 (330.0) 0.059 (1.50) 0.512 (13.00) 0.795 (20.20) 2.165 (55.00) 0.488 (12.4) 0.724 (18.4)

Physical Dimensions

8.75

8.50

7.62

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

A

0.65

6.00

PIN ONE

INDICATOR

1.75 MAX

1.50

1.25

R0.10

8° 0°

14

1

1.27

(0.33)

0.50

0.25

8

7

0.51

0.35

0.25

0.10

X45°

GAGE PLANE

0.36

B

4.00

3.80

1.70 1.27

LAND PATTERN RECOMMENDATION

M

BC A

SEE DETAIL A

0.10CC

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS. D) LANDPATTERN STANDARD:

SOIC127P600X145-14M E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13

5.60

0.25

0.19

0.90

0.50

SEATING PLANE

(1.04)

DETAIL A

SCALE: 20:1

Figure 3. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Physical Dimensions (Continued)

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Figure 4. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Physical Dimensions (Continued)

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

Figure 5. 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

Physical Dimensions (Continued)

M

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

0.43 TYP

0.65

1.65

0.45

R0.09 min

6.10

12.00°

TOP & BOTTO

A. CONFORMS TO JEDEC REGISTRATION MO-153,

VARIATION AB, REF NOTE 6

1.00

R0.09min

B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

AND TIE BAR EXTRUSIONS

D. DIMENSIONING AND TOLERANCES PER ANSI

Y14.5M, 1982

E. LANDPATTERN STANDARD: SOP65P640X110-14M

F. DRAWING FILE NAME: MTC14REV6

Figure 6. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions, speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

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Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

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ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ EcoSPARK

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EZSWITCH™ *

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Fairchild Fairchild Semiconductor FACT Quiet Series™ FACT FAST FastvCore™ FlashWriter

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*EZSWITCH™ and FlashWriter

FPS™

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FRFET Global Power Resource

SM

Green FPS™ Green FPS™e-Series™ GTO™ i-Lo™ IntelliMAX™ ISOPLANAR™ MegaBuck™ MICROCOUPLER™ MicroFET™ MicroPak™ MillerDrive™ Motion-SPM™ OPTOLOGIC OPTOPLANAR

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are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

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SupreMOS™ SyncFET™

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TinyBoost™ TinyBuck™ TinyLogic

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TINYOPTO™ TinyPower™ TinyPWM™ TinyWire™ µSerDes™

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UHC Ultra FRFET™ UniFET™ VCX™

74LCX14 — Low Voltage Hex Inverter with 5V Tolerant Schmitt Trigger Inputs

®

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

provided in the labeling, can be reasonably expected to result in a significant injury of the user.

PRODUCT STATUS DEFINITIONS Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design

This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

This datasheet contains preliminary data; supplementary data will be

Preliminary First Production

published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

This datasheet contains final specifications. Fairchild Semiconductor

No Identification Needed Full Production

reserves the right to make changes at any time without notice to improve the design.

This datasheet contains specifications on a product that has been

Obsolete Not In Production

discontinued by Fairchild Semiconductor. The datasheet is printed for reference information only.

Rev. I33