Page 1
INTEGRATED CIRCUITS
74LVC109
Dual JK
flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Mar 18
IC24 Data Handbook
1998 Apr 28
Page 2
Philips Semiconductors Product specification
74L VC109Dual JK flip-flop with set and reset; positive-edge trigger
FEA TURES
•Wide supply voltage range of 1.2 to 3.6 V
•In accordance with JEDEC standard no. 8-1A.
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Output capability: standard
•I
category: flip-flops
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr = t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
f
max
C
C
I
PD
Maximum clock frequency 250 MHz
Input capacitance 5.0 pF
Power dissipation capacitance per flip-flop VI = GND to V
NOTE:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD × V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
Σ (C
× V
L
2
× fi Σ (CL × V
CC
2
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
2
× fo) where:
CC
CL = 50 pF;
VCC = 3.3 V
DESCRIPTION
The 74LVC109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LVC109 is a dual positive-edge triggered JK
featuring individual J, K
) inputs; also complementary Q and Q outputs.
(R
D
inputs, clock (CP) inputs, set (SD) and reset
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K
inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation. The JK design allows operation as a
D-type flip-flop by tying the J and K
inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
4.0
4.5
4.5
CC
1
27 pF
-type flip-flop
inputs must
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic SO –40°C to +85°C 74LVC109 D 74LVC109 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +85°C 74LVC109 DB 74LVC109 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC109 PW 74LVC109PW DH SOT403-1
PIN CONFIGURATION
1R
1
D
1J
2
1K
3
1CP
4
1S
5
D
6
1Q
7
1Q
GND
1998 Apr 28 853–1947 19308
16
15
14
13
12
11
10
98
SV00517
V
2R
2J
2K
2CP
2S
2Q
2Q
CC
D
D
PIN DESCRIPTION
PIN
NUMBER
1, 15 1RD, 2R
2, 14, 3, 13 1J, 2J, 1K, 2K
4, 12 1CP, 2CP
5, 11 1S
6, 10 1Q, 2Q True flip-flop outputs
7, 9 1Q, 2Q Complement flip-flop outputs
8 GND Ground (O V)
16 V
2
SYMBOL FUNCTION
Asynchronous reset input
D
(active LOW)
Synchronous inputs;
flip-flops 1 and 2
Clock input
(LOW-to-HIGH, edge-triggered)
Asynchronous set inputs
(active LOW)
Positive supply voltage
CC
2S
D,
D
Page 3
Philips Semiconductors Product specification
Dual JK
flip-flop with set and reset; positive-edge trigger
LOGIC SYMBOL (IEEE/IEC)
5
S
2
1J
4
C1
3
1K
1
R
(a) (b)
610
79
LOGIC SYMBOL
11
5
1S
2S
D
74LVC109
FUNCTIONAL DIAGRAM
11
S
14
1J
12
13
15
D
C1
1K
R
SV00519
5
1S
D
S
D
1J
2
1CP
4
1K
3
1R
D
1
11
2S
D
2J
14
2CP
12
2K
13
2R
15
D
J
CP
K
J
K
CP
R
S
R
Q
FF1
Q
D
D
Q
FF2
Q
D
1Q
1Q
2Q
10
2Q
SV00520
6
7
9
14 2J
4 1CP
12 2CP
13 2K
LOGIC DIAGRAM
2 1J
3 1K
J
CP
K
CP
1Q 6
Q
2Q 10
7
1Q
Q
2Q
9
2R
1R
D
D
15
1
SV00518
C
K
J
S
R
C
C
C
C
C
C
C
C
Q
Q
1998 Apr 28
C
SV00521
3
Page 4
Philips Semiconductors Product specification
OPERATING MODES
SYMBOL
PARAMETER
CONDITIONS
UNIT
V
V
mW
Dual JK
flip-flop with set and reset; positive-edge trigger
74LVC109
FUNCTION TABLE
INPUTS OUTPUTS
nS
D
nR
D
nCP nJ nK nQ nQ
Asynchronous set L H X X X H L
Asynchronous reset H L X X X L H
Undetermined L L X X X H H
Toggle H H ↑ h l q q
Load “0” (reset) H H ↑ l l L H
Load “1” (set) H H ↑ h h H L
Hold “no change” H H ↑ l h q q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
X = don’t care
↑ = LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
DC supply voltage (for max. speed performance) 2.7 3.6
CC
DC supply voltage (for low-voltage applications) 1.2 3.6
T
V
V
amb
tr, t
DC input voltage range 0 5.5 V
I
DC output voltage range 0 V
O
Operating free-air temperature range –40 +85 °C
Input rise and fall times
f
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
0
0
CC
20
10
V
ns/V
ABSOLUTE MAXIMUM RATINGS
1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
, I
GND
CC
T
stg
DC supply voltage –0.5 to +6.5 V
DC input diode current VIt 0 –50 mA
DC input voltage Note 2 –0.5 to +5.5 V
DC output diode current V
DC output voltage Note 2 –0.5 to VCC +0.5 V
DC output source or sink current VO = 0 to V
DC VCC or GND current "100 mA
Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
uVCC or VO t 0 "50 mA
O
CC
"50 mA
Power dissipation per package
P
TOT
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
4
Page 5
Philips Semiconductors Product specification
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
V
IIInput leakage current
V
V
GND
"0.1
"5µA
Dual JK
flip-flop with set and reset; positive-edge trigger
74LVC109
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. V oltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
LOW level output voltage
OL
p
I
CC
∆I
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current per
CC
input pin
NOTE:
1. All typical values are at V
p
p
p
= 3.3V and T
CC
amb
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL; IO = –12mA VCC*0.5
VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
IO = –12mA VCC*0.6
IL;
IO = –24mA VCC*1.0
IL;
VCC = 2.7V; VI = VIH or VIL; IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
IO = 24mA 0.55
IL;
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
= 25°C.
CC
CC
V
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF; RL = 500; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT
t
PHL/tPLH
Propagation delay
nCP to nQ, nQ
Propagation delay
t
PLH
nSD to nQ
nRD to nQ
Propagation delay
t
t
f
PHL
t
W
t
W
rem
t
su
t
h
max
nSD to nQ
nRD to nQ
Clock pulse width
HIGH or LOW
Set or reset pulse width
HIGH or LOW
Removal time
nS
nRD to nCP
D,
Set-up time
nJ, nK to CP
Hold time
nJ, nK to nCP
Maximum clock pulse
frequency
NOTE:
1. These typical values are at V
= 3.3V and T
CC
amb
= –40C to +85C
amb
LIMITS
MIN TYP
1
MAX MIN
TYP
NO TAG
MAX
Figures 1, 3 4.3 7.5 8.5 ns
Figures 2, 3 4.5 8.0 9.0 ns
Figures 2, 3 5.2 9.0 10 ns
Figure 1 3.3 2.0 ns
Figure 2 3.0 ns
Figure 2 3.0 ns
Figure 1 2.5 ns
Figure 1 2.0 ns
Figure 1 150 225 MHz
= 25°C.
1998 Apr 28
5
Page 6
Philips Semiconductors Product specification
Dual JK
flip-flop with set and reset; positive-edge trigger
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V; VM = 0.5 × VCC at VCC < 2.7 V.
and VOH are the typical output voltage drop that occur with the output load.
V
OL
V
I
nJ, nK
INPUT
GND
nCP
INPUT
GND
V
OH
nQ
OUTPUT
V
OL
V
OH
nQ
OUTPUT
V
OL
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK
V
M
t
su
t
h
V
I
V
t
t
M
PHL
PLH
1/f
max
t
W
V
M
V
M
t
su
t
h
t
t
to nCP set-up,
the nCP to nJ, nK
hold times
and the maximum clock pulse frequency.
PLH
PHL
SV00522
74LVC109
V
l
nCP
INPUT
GND
V
l
nS
D
V
INPUT
GND
nR
INPUT
GND
V
OUTPUT
V
V
OUTPUT
V
OH
nQ
OH
nQ
V
l
D
OL
OL
M
t
t
W
t
PLH
V
M
t
PHL
V
M
rem
t
W
V
M
t
PHL
t
PLH
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths
and the nR
, nSD to nCP removal time.
D
V
M
t
rem
SV00523
TEST CIRCUIT
PULSE
GENERATOR
Test Circuit for Outputs
SWITCH POSITION
TEST S
t
PLH/tPHL
V
l
1
Open
t
S
V
cc
V
O
D.U.T.
R
T
C
L
1
2 < V
CC
Open
GND
R
L
R
L
90%
NEGATIVE
PULSE
POSITIVE
PULSE
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
W
V
M
(t
)
f
(tr)t
V
M
t
W
90%
10%
V
I
0V
(tr)
t
TLH
(tf)
THL
V
I
0V
VM = 1.5V
Input Pulse Definition
DEFINITIONS
V
CC
< 2.7V
2.7–3.6V
≥ 4.5 V V
V
I
V
CC
2.7V
CC
Figure 3. Load circuitry for switching times.
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance:
See AC CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
OUT
SV00904
of
1998 Apr 28
6
Page 7
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LVC109
1998 Apr 28
7
Page 8
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74LVC109
1998 Apr 28
8
Page 9
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74LVC109
1998 Apr 28
9
Page 10
Philips Semiconductors Product specification
Dual JK flip-flop with set and reset; positive-edge trigger
DEFINITIONS
74LVC109
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code Date of release: 05-96
Document order number: 9397-750-04489
1997 Mar 18
10
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