The 74LVC00A is a low voltage CMOS QUAD
2-INPUT NAND GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology. It is ideal for 1.65 to 3.6 V
2
MOS
CC
TSSOPSOP
ORDER CODES
PACKAGETUBET & R
SOP74LVC00AM74LVC00AMTR
TSSOP74LVC00ATTR
operations and low power and low noise
applications.
It can be interfaced to 5V signal environment for
inputs in mixed 3.3/5V system.
It has more speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/8February 2002
Page 2
74LVC00A
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION TRUTH TABLE
PIN NoSYMBOLNAME AND FUNCTION
1, 4, 9, 121A to 4AData Inputs
2, 5, 10, 131B to 4BData Inputs
3, 6, 8, 111Y to 4YData Outputs
7GNDGround (0V)
14
V
CC
Positive Supply Voltage
ABY
LLH
LHH
HLH
HHL
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
V
I
I
OK
I
I
or I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
absolute ma xim um rating must be obse rved
O
2) V
< GND
O
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage (VCC = 0V)
O
DC Output Voltage (High or Low State) (note 1)-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current (note 2)
DC Output Current
O
DC VCC or Ground Current per Supply Pin
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0V
-0.5 to +7.0V
-0.5 to +7.0V
V
- 50mA
- 50mA
± 50mA
± 100mA
-65 to +150°C
300°C
2/8
Page 3
74LVC00A
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
V
I
OH
I
OH
I
OH
I
OH
T
dt/dvInput Rise and Fall Time (note 2)0 to 10ns/V
1) Truth T abl e guarante ed: 1.2V to 3.6 V
2) V
from 0.8V to 2V at VCC = 3.0V
IN
DC SPECIFICATIONS
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage (VCC = 0V)
O
Output Voltage (High or Low State)0 to V
O
, I
High or Low Level Output Current (VCC = 3.0 to 3.6V)
OL
, I
High or Low Level Output Current (VCC = 2.7 to 3.0V)
OL
, I
High or Low Level Output Current (VCC = 2.3 to 2.7V)
OL
, I
High or Low Level Output Current (VCC = 1.65 to 2.3V)
OL
Operating Temperature
op
Test ConditionValue
1.65 to 3.6V
0 to 5.5V
0 to 5.5V
CC
± 24mA
± 12mA
± 8mA
± 4mA
-55 to 125°C
V
SymbolParameter
V
V
V
V
I
I
CC
∆I
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
I
Input Leakage
I
Current
Power Off Leakage
off
Current
Quiescent Supply
Current
ICC incr. per Input
CC
V
CC
(V)
1.65 to 1.95
-40 to 85 °C-55 to 125 °C
Min.Max.Min.Max.
0.65V
CC
0.65V
CC
2.3 to 2.71.71.7
2.7 to 3.622
1.65 to 1.95
0.35V
CC
0.35V
2.3 to 2.70.70.7
2.7 to 3.60.80.8
1.65 to 3.6
1.65
2.3
2.7
3.0
3.0
1.65 to 3.6
1.65
2.3
2.7
3.0
3.6
0
3.6
2.7 to 3.6
IO=-100 µAVCC-0.2VCC-0.2
I
=-4 mA
O
I
=-8 mA
O
I
=-12 mA
O
I
=-18 mA
O
I
=-24 mA
O
IO=100 µA
I
=4 mA
O
I
=8 mA
O
I
=12 mA
O
I
=24 mA
O
= 0 to 5.5V
V
I
or VO = 5.5V
V
I
VI = VCC or GND
V
or VO = 3.6 to
I
5.5V
VIH = VCC-0.6V
1.21.2
1.71.7
2.22.2
2.42.4
2.22.2
0.20.2
0.450.45
0.70.7
0.40.4
0.550.55
± 5± 5µA
1010µA
1010
± 10± 10
500500µA
Unit
V
CC
V
V
V
µA
3/8
Page 4
74LVC00A
DYNAMIC SWITCHING CHARACTERISTICS
Test ConditionValue
T
SymbolParameter
V
OLP
V
OLV
1) Number of output defined as "n". Measured with "n-1" outputs switc hi ng from HIGH to LOW or LOW to H IGH. The remai ning outp ut is
measur ed i n the LOW sta te.
Dynamic Low Level Quiet
Output (note 1)
V
(V)
3.3
CC
= 50pF
C
L
V
= 0V, VIH = 3.3V
IL
Min.Typ.Max.
AC ELECTRICAL CHARACTERISTICS
Test ConditionValue
= 25 °C
A
0.8
-0.8
Unit
V
SymbolParameter
t
PLH tPHL
Propagation Delay
Time
V
(V)
CC
C
(pF)
R
t
L
(Ω)
= t
L
s
(ns)
-40 to 85 °C-55 to 125 °C
r
Min.Max.Min.Max.
1.65 to 1.953010002.09.012
2.3 to 2.7305002.06.08.0
2.7505002.55.16.1
Unit
ns
3.0 to 3.6505002.514.315.1
t
OSLH
t
OSHL
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW ( t
2) Param eter guaranteed by design
Output To Output
Skew Time (note1,
2)
2.7 to 3.611ns
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|
CAPACITIVE CHARACTERISTICS
Test ConditionValue
= 25 °C
SymbolParameter
V
CC
(V)
C
C
Input Capacitance
IN
Power Dissipation Capacitance
PD
(note 1)
1.8fIN = 10MHz27
3.333
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
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