Page 1
INTEGRATED CIRCUITS
74LVC00A
Quad 2-input NAND gate
Product specification
Supersedes data of 1997 Aug 11
IC24 Data Handbook
1998 Apr 28
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Philips Semiconductors Product specification
Data inputs
74L VC00AQuad 2-input NAND gate
FEA TURES
•Wide supply range of 1.2V to 3.6V
•Complies with JEDEC standard no. 8-1A
•Inputs accept voltages up to 5.5V
•CMOS low power consumption
•Direct interface with TTL levels
•5-volt tolerant inputs, for interfacing with 5-volt logic
DESCRIPTION
The 74LVC00A is a high-performance, low power, low-voltage,
Si-gate CMOS device and superior to most advanced CMOS
compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This feature
allows the use of these devices as translators in a mixed 3.3 V/5 V
environment.
Schmitt-trigger action at all inputs makes the circuit tolerant for
slower input rise and fall times.
The 74LVC00A provides the 2-input NAND function.
QUICK REFERENCE DATA
GND = 0 V; T
SYMBOL
NOTES:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
L
= 25°C; tr =tf 2.5 ns
amb
t
PHL
t
PLH
C
I
C
PD
2
CC
2
V
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
nA, nB to nY
CL = 50 pF;
VCC = 3.3 V
3.0 ns
Input capacitance 5.0 pF
Power dissipation capacitance per gate VI = GND to V
x fi (CL V
2
fo) where:
CC
CC
1
28 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
14-Pin Plastic SO –40°C to +85°C 74LVC00A D 74LVC00A D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +85°C 74LVC00A DB 74LVC00A DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC00A PW 74LVC00APW DH SOT402-1
PIN CONFIGURATION
1A
1
1B
2
1Y
3
2A
4
2B
5
2Y
6
GND
LOGIC SYMBOL (IEEE/IEC)
1
2
4
5
9
10
12
13
&
&
&
&
SY00034
SV00378
LOGIC SYMBOL
1A
14
V
CC
4B
13
4A
12
4Y
11
3B
10
3A
9
3Y
87
1
1B
2
2A
4
2B
5
3A
9
3B
10
4A
12
4B
13
1Y
3
2Y
6
3Y
8
4Y
11
SY00035
PIN DESCRIPTION
PIN
3
6
NUMBER
1, 4, 9, 12 1A – 4A
2, 5, 10, 13 1B – 4B
3, 6, 8, 11 1Y – 4Y Data outputs
8
7 GND Ground (0 V)
14 V
11
SYMBOL NAME AND FUNCTION
p
CC
Positive supply voltage
1998 Apr 28 853-2017 19310
2
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Philips Semiconductors Product specification
SYMBOL
PARAMETER
CONDITIONS
UNIT
mW
74LVC00AQuad 2-input NAND gate
LOGIC DIAGRAM (ONE GATE)
A
Y
B
SV00379
RECOMMENDED OPERATING CONDITIONS
T
V
V
tr, t
CC
CC
V
V
amb
O
DC supply voltage (for max. speed performance) 2.7 3.6 V
DC supply voltage (for low-voltage applications) 1.2 3.6 V
DC Input voltage range 0 5.5 V
I
DC output voltage range 0 V
Operating ambient temperature range in free-air –40 +85 °C
Input rise and fall times
f
FUNCTION TABLE
nA nB nY
L L H
L H H
H L H
H H L
NOTES:
H = HIGH voltage level
L =LOW voltage level
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
INPUTS OUTPUTS
LIMITS
MIN MAX
CC
0
0
20
10
V
ns/V
ABSOLUTE MAXIMUM RATINGS
1
Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
, I
GND
CC
T
stg
DC supply voltage (for max. speed
performance)
DC input diode current VI 0 –50 mA
DC input voltage Note 2 –0.5 to +5.5 V
DC output diode current V
DC output voltage Note 2 –0.5 to VCC + 0.5 V
DC output source or sink current VO = 0 to V
DC VCC or GND current 100 mA
Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
–0.5 to +6.5 V
VCC or VO 0 50 mA
O
CC
50 mA
Power dissipation per package
P
TOT
– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
– plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 28
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Philips Semiconductors Product specification
VIHHIGH level Input voltage
V
VILLOW level Input voltage
V
VOHHIGH level output voltage
V
IIInput leakage current
V
V
GND
"0.1
"5µA
74LVC00AQuad 2-input NAND gate
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
LOW level output voltage
OL
p
I
CC
∆I
Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 10 µA
Additional quiescent supply current
CC
per input pin
NOTES:
1. All typical values are at V
p
p
p
= 3.3V and T
CC
amb
VCC = 1.2V V
VCC = 2.7 to 3.6V 2.0
VCC = 1.2V GND
VCC = 2.7 to 3.6V 0.8
VCC = 2.7V; VI = VIH or VIL;IO = –12mA VCC*0.5
VCC = 3.0V; VI = VIH or VIL;IO = –100µA VCC*0.2 V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
= –18mA VCC*0.6
IL;IO
= –24mA VCC*0.8
IL;IO
VCC = 2.7V; VI = VIH or VIL;IO = 12mA 0.40
VCC = 3.0V; VI = VIH or VIL;IO = 100µA 0.20
VCC = 3.0V; VI = VIH or V
;
= 3.6V;
CC
= 5.5V or
I
= 24mA 0.55
IL;IO
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA
= 25°C.
CC
CC
V
AC CHARACTERISTICS
GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF
SYMBOL PARAMETER WAVEFORM
t
/
PHL
t
PLH
Propagation delay
nA, nB to nY
1, 2 1.5 3.0 5.0 1.5 3.4 5.8 11 ns
NOTE:
1. These typical values are at V
= 3.3V and T
CC
amb
= 25°C.
AC WAVEFORMS
VM = 1.5 V at VCC w 2.7 V
= 0.5 VCC at VCC < 2.7 V
V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
V
I
nA, nB INPUT
GND
V
OH
nY OUTPUT
V
OL
Waveform 1. Input (nA) to output (nY) propagation delays.
V
M
t
PHL t
V
M
LIMITS
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V
MIN TYP1MAX MIN TYP MAX TYP
TEST CIRCUIT
V
CC
V
O
C
L
t
PLH/tPHL
50pF
Test S
PLH
SV00377
V
PULSE
GENERATOR
I
R
T
V
CC
t 2.7V V
2.7V – 3.6V 2.7V
V
D.U.T.
I
CC
Waveform 2. Load circuitry for switching times.
S
500Ω
500Ω
Open
1
1
UNIT
2 < V
Open
GND
SY00077
CC
1998 Apr 28
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Philips Semiconductors Product specification
74LVC00AQuad 2-input NAND gate
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
1998 Apr 28
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Philips Semiconductors Product specification
74LVC00AQuad 2-input NAND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
1998 Apr 28
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Philips Semiconductors Product specification
74LVC00AQuad 2-input NAND gate
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
1998 Apr 28
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Philips Semiconductors Product specification
74LVC00AQuad 2-input NAND gate
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04476
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