Datasheet 74LV74PW, 74LV74N, 74LV74DB, 74LV74D Datasheet (Philips)

INTEGRATED CIRCUITS

74LV74

Dual D-type flip-flop with set and reset; positive-edge trigger

Product specification Supersedes data of 1996 Nov 07 IC24 Data Handbook

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1998 Apr 20

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

FEA TURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce)  0.8V @ VCC = 3.3V,

OLP

= 25°C

(output VOH undershoot)  2V @ VCC = 3.3V,

OHV

= 25°C

•Output capability: standard

•I

category: flip-flops

CC

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

f

max

C

I

C

PD

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW)

PD

= CPD  V

P

D

= input frequency in MHz; CL = output load capacitance in pF;

f

i

f

= output frequency in MHz; VCC = supply voltage in V;

o

 (C

2. The condition is V

= 25°C; tr =tf 2.5 ns

amb

CC

2

 V

L

 fo) = sum of the outputs.

CC

Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ

Maximum clock frequency Input capacitance 3.5 pF

Power dissipation capacitance per flip-flop Notes 1 and 2 24 pF

2

x fi  (CL  V

= GND to V

I

= 2.7V and VCC = 3.6V

CC

PARAMETER CONDITIONS TYPICAL UNIT

CL = 15pF V

CC

CL = 15pF VCC = 3.3V

2

 fo) where:

CC

74L V74

DESCRIPTION

The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74.

The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (S inputs; also complementary Q and Q

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

= 3.3V

outputs.

11 14 14

76 MHz

) and (RD)

D

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

14-Pin Plastic DIL –40°C to +125°C 74L V74 N 74LV74 N SOT27-1 14-Pin Plastic SO –40°C to +125°C 74L V74 D 74LV74 D SOT108-1 14-Pin Plastic SSOP Type II –40°C to +125°C 74LV74 DB 74LV74 DB SOT337-1 14-Pin Plastic TSSOP Type I –40°C to +125°C 74L V74 PW 74LV74PW DH SOT402-1

PIN DESCRIPTION

NUMBER

1, 13 1R 2, 12 1D, 2D Data inputs 3, 11 1CP, 2CP

4, 10 1S 5, 9 1Q, 2Q True flip-flop outputs

6, 8 1Q 7 GND Ground (0V) 14 V

SYMBOL FUNCTION

D,

,

CC

Asynchronous reset-direct input

2R

D

(active-LOW)

Clock input (LOW-to-HIGH), edge-triggered)

Asynchronous set-direct input

2S

D

(active-LOW)

2Q Complement flip-flop outputs

Positive supply voltage

FUNCTION TABLE

INPUTS OUTPUTS

S

D

L

H

L

R

D

H

L L

CP D Q Q

X X X

INPUTS OUTPUTS

S

D

H H

H = HIGH voltage level L = LOW voltage level X = don’t care  = LOW-to-HIGH CP transition Q

= state after the next LOW-to-HIGH CP transition

n+1

R

D

H H

CP D Q

 

L H

H

L

H

n+1

L

H

L H H

Q

n+1

H

L

1998 Apr 20 853-1888 19258

2

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

PIN CONFIGURATION

1R

1D

1CP

1S

1Q

GND

1

D

2

3

4

D

5

6

7

14

13

12

11

10

9

8

SV00330

V

2R

2D

2CP

2S

2Q

CC

D

LOGIC SYMBOL

10

4

2S

1S

D

S

21D 1Q 5

12 2D 2Q 9

3 1CP

11 2CP

D

CP

R

D

1RD2R

113

Q

FF

Q

1Q 2Q 8

D

SV00331

74LV74

6

LOGIC SYMBOL (IEEE/IEC)

4 3 2 1

10 11

12 13

S

C1 1D R

S

C2 2D R

SV00332

FUNCTIONAL DIAGRAM

5

6

9

8

4

3

1

10

13

1S

1D2

1CP

1R

2S

2D12 2CP11

2R

D

S

D

DQ CP FF1

Q

R

D

S

D

DQ CP FF2

Q

R

D

SV00333

1Q

2Q 9

2

Q

5

6

8

1998 Apr 20

3

Philips Semiconductors Product specification

P

mW

Dual D-type flip-flop with set and reset; positive edge-trigger

LOGIC DIAGRAM (ONE FLIP-FLOP)

C

CP

C

D

C

R

D

S

D

C

74LV74

Q

C

Q

SV00334

RECOMMENDED OPERA TING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

V

CC

V

T

amb

tr, t

NOTE:

1. The LV is guaranteed to function down to V

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

V

CC

±I

IK

±I

OK

±I

O

±I

GND

±I

CC

T

stg

tot

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC supply voltage See Note1 1.0 3.3 5.5 V Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free air

Input rise and fall times except for

f

Schmitt-trigger inputs

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

CC

See DC and AC characteristics

VCC = 1.0V to 2.0V V

= 2.0V to 2.7V

CC

VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V

–40 –40

– – – –

+85

+125

– – –

500 200 100

–

1, 2

PARAMETER CONDITIONS RATING UNIT

DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current

– standard outputs DC VCC or GND current for types with

,

–standard outputs 50

–0.5V < VO < VCC + 0.5V

25

Storage temperature range –65 to +150 °C Power dissipation per package for temperature range: –40 to +125°C –plastic DIL above +70°C derate linearly with 12mW/K 750 –plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500 –plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400

50

CC CC

V V

°C

ns/V

mA

1998 Apr 20

4

Philips Semiconductors Product specification

V

HIGH l

t

voltage all out uts

V

g

V

LOW l

t

voltage all out uts

V

g

V

Dual D-type flip-flop with set and reset; positive edge-trigger

DC CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

SYMBOL P ARAMETER TEST CONDITIONS

MIN TYP

VCC = 1.2V 0.9 0.9

HIGH level Input

IH

voltage

LOW level Input

IL

voltage

V

OH

evel outpu

;

HIGH level output voltage;

OH

STANDARD outputs

V

OL

evel outpu

;

LOW level output voltage;

OL

STANDARD outputs

Input leakage

I

current

CC

Quiescent supply current; flip-flops

I

Additional

CC

quiescent supply current per input

∆I

NOTE:

1. All typical values are measured at T

VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*V VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 4.5 to 5.5 0.3*V VCC = 1.2V; VI = VIH or V VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V VCC = 1.2V; VI = VIH or V

VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V;VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V

–IO = 100µA 1.2

IL;

–IO = 100µA 1.8 2.0 1.8

IL;

–IO = 100µA 2.5 2.7 2.5

IL;

–IO = 100µA 2.8 3.0 2.8

IL;

–IO = 100µA 4.3 4.5 4.3

IL;

–IO = 6mA 2.40 2.82 2.20

IL;

–IO = 12mA 3.60 4.20 3.50

IL;

IO = 100µA 0

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 6mA 0.25 0.40 0.50

IL;

IO = 12mA 0.35 0.55 0.65

IL;

VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA

VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80 µA

VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA

= 25°C.

amb

74LV74

LIMITS

-40°C to +85°C -40°C to +125°C

1

MAX MIN MAX

CC

0.7*V

CC

0.3*V

CC

UNIT

CC

V

1998 Apr 20

5

Philips Semiconductors Product specification

P

nCP to nQ, nQ

P

nS

D

nQ

P

nR

D

nQ

t

Figure 1

ns

t

Figure 2

ns

R

set or reset

Set

nD to nCP

Hold ti

nD to nCP

f

Figure 1

MHz

Dual D-type flip-flop with set and reset; positive edge-trigger

AC CHARACTERISTICS

GND = 0V; tr = tf  2.5ns; CL = 50pF; RL = 1KΩ

SYMBOL

t

PHL/tPLH

t

PHL/tPLH

t

PHL/tPLH

W

t

rem

t

su

t

h

max

PARAMETER WAVEFORM

ropagation delay

to nQ,

ropagation delay

to nQ,

Figures, 1, 3

Figures 2, 3

Clock pulse width HIGH to LOW

Set or reset pulse width LOW

emoval time

-up time

me

Figure 2

Figure 1

Maximum clock pulse frequency

NOTE:

1. Unless otherwise stated, all typical values are at T

2. Typical value measured at V

3. Typical value measured at V

CC CC

= 3.3V. = 5.0V.

amb

CONDITION

= 25°C.

LIMITS

–40 to +85 °C

LIMITS

–40 to +125 °C

VCC(V) MIN TYP1MAX MIN MAX

1.2 – 70 – – –

2.0 – 24 44 – 56

2.7 – 18 28 – 41

3.0 to 3.6 – 13

4.5 to 5.5 – 9.5

2

26 – 33

3

17 – 23

1.2 – 90 – – –

2.0 – 31 46 – 58

2.7 – 23 34 – 43

3.0 to 3.6 – 17

4.5 to 5.5 – 12

2

27 – 34

3

19 – 24

1.2 – 90 – – –

2.0 – 31 46 – 58

2.7 – 23 34 – 43

3.0 to 3.6 – 17

4.5 to 5.5 – 12

2

27 – 34

3

19 – 24

2.0 34 10 – 41 –

2.7 25 8 – 30 –

3.0 to 3.6 20 7

4.5 to 5.5 15 6

2 3

– 24 – – 18 –

2.0 34 10 – 41 –

2.7 25 8 – 30 –

3.0 to 3.6 20 7

4.5 to 5.5 15 6

2 3

– 24 – – 18 –

1.2 – 5 – – –

2.0 14 2 – 15 –

2.7 10 1 – 11 –

3.0 to 3.6 8 1

4.5 to 5.5 6 1

2 3

– 9 – – 7 –

1.2 – 10 – – –

2.0 22 4 – 26 –

2.7 12 3 – 15 –

3.0 to 3.6 8 2

4.5 to 5.5 6 1

2 2

– 10 – – 8 –

1.2 – –10 – – –

2.0 3 –2 – 3 –

2.7 3 –2 – 3 –

3.0 to 3.6 3 –2

4.5 to 5.5 3 –2

2 3

– 3 – – 3 –

2.0 14 40 – 12 –

2.7 50 90 – 40 –

3.0 to 3.6 60 100

4.5 to 5.5 70 110

2

– 48 –

3

– 56 –

74LV74

UNIT

ns

1998 Apr 20

6

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

AC WAVEFORMS

VM = 1.5V at VCC  2.7V  3.6V V

= 0.5 * VCC at V

M

and V

V

OL

output load.

nCP INPUT

nQ OUTPUT V

nQ OUTPUT

OH

GND

V

V V

V

I

V

I

OH

OL

OH

OL

 2.7V and  4.5V

CC

are the typical output voltage drop that occur with the

VMnD INPUT

t

h

t

su

V

t

PHL

1/f

max

M

t

W

M

V

M

t

PLH

t

h

t

su

t

PLH

t

PHL

TEST CIRCUIT

V

cc

V

PULSE

GENERATOR

DEFINITIONS

RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to Z

TEST

t

PLH/tPHL

Figure 3. Load circuitry for switching times

l

D.U.T.

R

T

Test Circuit for Outputs

V

CC

< 2.7V

2.7–3.6V ≥ 4.5 V V

V

2.7V

CC

74LV74

V

O

50pF

C

L

of pulse generators.

OUT

I

RL= 1k

SV00902

SV00335

Figure 1.The clock (nCP) to output (nQ, nQ) propagation

delays, the clock pulse width, the nD to nCP setup times, the

nCP to nD hold times, the output transition times and the

maximum clock pulse frequency

NOTE:

The shaded areas indicate when the input is permitted to change for predictable output performance.

V

I

nCP INPUT

GND

INPUT

nS

D

GND

nR

INPUT

D

GND

V

nQ OUTPUT

V

nQ OUTPUT

V

I

V

M

t

V

I

OH

OL

OH

OL

W

t

PLH

V

M

V

M

t

PHL

t

W

V

M

t

PHL

t

PLH

V

M

t

rem

SV00336

Figure 2.The set (nSD) and reset (nRD) input to output (nQ, nQ)

propagation delays, the set and reset pulse widths and the nR

to nCP removal time

1998 Apr 20

D

7

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

74LV74

1998 Apr 20

8

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74LV74

1998 Apr 20

9

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

74LV74

1998 Apr 20

10

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

74LV74

1998 Apr 20

11

Philips Semiconductors Product specification

Dual D-type flip-flop with set and reset; positive edge-trigger

DEFINITIONS

74LV74

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-04414

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