Page 1
INTEGRATED CIRCUITS
74LV595
8-bit serial-in/serial or parallel-out shift
register with output latches (3-State)
Product specification 1998 Apr 20
IC24 Data Handbook
Page 2
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
FEA TURES
•Optimized for Low Voltage applications: 1.0V to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8V at V
OLP
= 25°C
(output VOH undershoot) > 2V at V
OHV
= 25°C
= 2.7V and V
CC
CC
CC
CC
= 3.3V ,
= 3.3V ,
•8-bit serial input
•8-bit serial or parallel output
•Storage register with 3-State outputs
•Shift register with direct clear
•Output capability:
– parallel outputs; bus driver
– serial output; standard
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD V
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
2. The condition is V
= 25°C; tr =tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
SHCP to Q
STCP to Q
MR to Q
Maximum clock frequency SHCP, ST
Input capacitance 3.5 pF
Power dissipation capacitance per gate
2
x fi (CL V
= GND to V
I
7’
CC.
7’
7’
CC
2
fo) where:
= 3.6V
CP
APPLICATIONS
•Serial-to-parallel data conversion
•Remote control holding register
DESCRIPTION
The 74LV595 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT595.
The74L V595 is an 8-stage serial shift register with a storage register
and 3-State outputs. The shift register and storage register have
separate clocks.
Data is shifted on the positive-going transitions of the SH
The data in each register is transferred to the storage register on a
positive-going transition of the ST
connected together , the shift register will always be one clock pulse
ahead of the storage register.
The shift register has a serial input (D
(Q
) all for cascading. It is also provided with asynchronous reset
7’
(active LOW) for all 8 shift register stages. The storage register has
8 parallel 3-State bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE
LOW.
CL = 15pF
VCC= 3.3V 15
VCC = 3.3V
Notes 1 and 2
74L V595
input. If both clocks are
CP
) and a serial standard output
S
16
14
77 MHz
115 pF
CP
input.
) is
ns
ORDERING AND PACKAGE INFORMA TION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV595 N 74LV595 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV595 D 74LV595 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV595 DB 74LV595 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74L V595 PW 74LV595PW DH SOT403-1
1998 Apr 20 853-1987 19255
2
Page 3
Philips Semiconductors Product specification
FUNCTION
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
PIN DESCRIPTION
PIN
NUMBER
15, 1, 2, 3,
4, 5, 6, 7
8 GND Ground (0V)
9 Q
10 MR Master reset (active LOW)
11 SH
12 ST
13 OE Output enable input (active LOW)
14 D
16 V
SYMBOL FUNCTION
Q0 to Q7Parallel data output
Serial data output
7’
Shift register clock input
CP
Storage register clock input
CP
Serial data input
S
Positive supply voltage
CC
FUNCTION TABLE
INPUTS OUTPUTS
SH
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
Z = High impedance OFF-state
NC= No change
= LOW-to-HIGH clock transition
↓ = HIGH-to-LOW transition
CP
ST
OE MR D
CP
S
Q
7’
Qn
X X L L X L NC A LOW level on MR only affects the shift registers
X L L X L L Empty shift register loaded into storage register
X X H L X L Z Shift register clear. Parallel outputs in high-impedance OFF-states
X L H H Q
6’
X L H X NC Q
L H X Q
6’
NC
Q
n’
n’
PIN CONFIGURATION
Q
1
1
Q
2
2
Q
3
3
Q
4
4
Q
5
5
Q
6
6
Q
7
7
GND
8
Logic high level shifted into shift register stage 0. Contents of all shift
register stages shifted through, e.g. previous state of stage 6 (internal
Q
) appears on the serial output (Q7’)
6’
Contents of shift register stages (internal Qn’) are transferred to the
storage register and parallel output stages
Contents of shift register shifted through. Previous contents of the shift
register are transferred to the storage register and the parallel output
stages
16
15
14
13
12
11
10
9
SV00720
74LV595
V
CC
Q
0
D
S
OE
ST
CP
SH
CP
MR
Q
7’
1998 Apr 20
3
Page 4
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
LOGIC SYMBOL
14
11
SH
CP
D
S
MR OE
12
ST
CP
Q
7’
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
9
15
1
2
3
4
5
6
7
FUNCTIONAL DIAGRAM
74LV595
D
S
14
SH
CP
11
MR
10
ST
CP
12
OE
13
Q0Q1Q2Q3Q4Q5Q6Q
15 1 2 3 4 5 6 7
8–STAGE SHIFT
REGISTER
8–BIT STORAGE
REGISTER
3–STATE OUTPUTS
Q7’
9
7
10 13
LOGIC SYMBOL (IEEE/IEC)
13
12
10
11
14
SRG8
R
C1/
1D
EN3
2D
SV00723
C2
3
15
1
2
3
4
5
6
7
9
SV00724
SV00725
1998 Apr 20
4
Page 5
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
LOGIC DIAGRAM
SH
STAGE 0 STAGE 7
D
S
CP
MR
ST
CP
OE
D
FFO
CP
R
D
LATCH
CP
Q
Q
STAGES 1 to 6
DQ
D
FF7
CP
R
D
LATCH
CP
74LV595
Q
Q
Q7’
TIMING DIAGRAM
SHCP
DS
STCP
MR
OE
Q0
Q1
Q6
Q
0
Q1Q2Q3Q4Q5Q
6
Z–state
Z–state
Z–state
Q
7
SV00721
1998 Apr 20
Q7’
Q7
Z–state
SV00726
5
Page 6
Philips Semiconductors Product specification
HIGH l
t
voltage
LOW l
t
voltage
V
V
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP . MAX UNIT
V
CC
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
P
TOT
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC supply voltage See Note1 1.0 3.3 3.6 V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free
air
Input rise and fall times
f
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC =3.6V.
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
–40
–40
–
–
–
–
–
–
1, 2
PARAMETER CONDITIONS RATING UNIT
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
–0.5V < VO < VCC + 0.5V
– bus driver outputs
DC VCC or GND current for types with
,
–standard outputs
–bus driver outputs
Storage temperature range –65 to +150 °C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
74LV595
CC
CC
+85
+125
500
200
100
25
35
50
70
750
500
400
V
V
°C
ns/V
mA
mA
mW
DC CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOL P ARAMETER TEST CONDITIONS
MIN TYP
VCC = 1.2V 0.9 0.9
VCC = 2.0V 1.4 1.4
VCC = 2.7 to 3.6V 2.0 2.0
VCC = 1.2V 0.3 0.3
VCC = 2.0V 0.6 0.6
VCC = 2.7 to 3.6V 0.8 0.8
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
VCC = 3.0V;VI = VIH or V
–IO = 100µA 1.2
IL;
–IO = 100µA 1.8 2.0 1.8
IL;
–IO = 100µA 2.5 2.7 2.5
IL;
–IO = 100µA 2.8 3.0 2.8
IL;
–IO = 6mA 2.40 2.82 2.20 V
IL;
6
V
IH
V
IL
OH
V
OH
1998 Apr 20
evel Inpu
evel Inpu
HIGH level output
voltage; all outputs
HIGH level output
voltage;
STANDARD
outputs
LIMITS
-40°C to +85°C -40°C to +125°C
1
MAX MIN MAX
UNIT
V
V
Page 7
Philips Semiconductors Product specification
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
V
V
t
gy
Figure 1
ns
t
gy
Figure 2
ns
t
gy
Figure 5
ns
t
enable time
Figure 3
ns
OE to Q
n
t
disable time
Q
Figure 3
ns
OE to Q
n
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
DC CHARACTERISTICS (Continued)
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
HIGH level output
V
voltage; BUS driver
OH
outputs
VCC = 3.0V;VI = VIH or V
VCC = 1.2V; VI = VIH or V
LOW level output
OL
voltage; all outputs
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
VCC = 3.0V;VI = VIH or V
LOW level output
OL
voltage;
STANDARD
VCC = 3.0V;VI = VIH or V
V
outputs
LOW level output
V
I
I
voltage; BUS driver
OL
outputs
Input leakage
I
I
current
3-State output
OZ
OFF-state current
Quiescent supply
CC
current; MSI
VCC = 3.0V;VI = VIH or V
VCC = 3.6V; VI = VCC or GND 1.0 1.0 µA
VCC = 3.6V; VI = VIH or V
VO = VCC or GND
VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 160 µA
Additional
CC
quiescent supply
current per input
VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 8mA 2.40 2.82 2.20 V
IL;
IO = 100µA 0
IL;
IO = 100µA 0 0.2 0.2
IL;
IO = 100µA 0 0.2 0.2
IL;
IO = 100µA 0 0.2 0.2
IL;
IO = 6mA 0.25 0.40 0.50 V
IL;
IO = 8mA 0.20 0.40 0.50 V
IL;
IL;
74LV595
LIMITS
-40°C to +85°C -40°C to +125°C
5 10 µA
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
PHL/tPLH
PHL/tPLH
PHL
PZH/tPZL
PHZ/tPLZ
PARAMETER WAVEFORM
Propagation delay
SHCP to Q7’
Propagation delay
STCP to Q
n
Propagation delay
MR to Q7’
3-State output
OE to Q
3-State output
OE to
CONDITION
LIMITS
–40 to +85 °C
LIMITS
–40 to +125 °C
VCC(V) MIN TYP1MAX MIN MAX
1.2 – 95 – – –
2.0 – 32 61 – 75
2.7 – 24 45 – 55
3.0 to 3.6 – 18
2
36 – 44
1.2 – 100 – – –
2.0 – 34 65 – 77
2.7 – 25 48 – 56
3.0 to 3.6 – 19
2
38 – 45
1.2 – 85 – – –
2.0 – 29 56 – 66
2.7 – 21 41 – 49
3.0 to 3.6 – 16
2
33 – 33
1.2 – 85 – – –
2.0 – 29 56 – 66
2.7 – 21 41 – 49
3.0 to 3.6 – 16
2
33 – 39
1.2 – 65 – – –
2.0 – 24 40 – 49
2.7 – 18 32 – 37
3.0 to 3.6 – 14
2
26 – 30
UNIT
1998 Apr 20
7
Page 8
Philips Semiconductors Product specification
Shift clock
width HIGH or LOW
St
width HIGH or LOW
Mast
width LOW
t
Figure 4
ns
t
Figure 2
ns
t
Figure 4
ns
t
Figure 5
ns
Maximum clock
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
t
W
t
W
t
W
su
su
h
rem
PARAMETER WAVEFORM
pulse
orage clock pulse
er reset pulse
Figure 1
Figure 2
Figure 5
Set-up time
DS to SH
CP
Set-up time
SHCP to ST
CP
Hold time
DS to SH
CP
Removal time
MR to SH
CP
Maximum clock
f
max
pulse frequency
SHCP or ST
CP
Figure 1, 2
NOTES:
1. Unless otherwise stated, all typical values are at T
2. Typical value measured at V
= 3.3V.
CC
amb
CONDITION
VCC(V) MIN TYP1MAX MIN MAX
2.0 34 10 – 41 –
2.7 25 8 – 30 –
3.0 to 3.6 20 6
2.0 34 7 – 41 –
2.7 25 5 – 30 –
3.0 to 3.6 20 4
2.0 34 10 – 41 –
2.7 25 8 – 30 –
3.0 to 3.6 20 6
1.2 – 40 – – –
2.0 26 14 – 31 –
2.7 19 10 – 23 –
3.0 to 3.6 15 8
1.2 – 40 – – –
2.0 26 14 – 31 –
2.7 19 10 – 23 –
3.0 to 3.6 15 8
1.2 – –10 – – –
2.0 5 –4 – 5 –
2.7 5 –3 – 5 –
3.0 to 3.6 5 –2
1.2 – –35 – – –
2.0 5 –12 – 5 –
2.7 5 –9 – 5 –
3.0 to 3.6 5 –7
2.0 14 40 – 12 –
2.7 19 58 – 16 –
3.0 to 3.6 24 70
= 25°C.
LIMITS
–40 to +85 °C
2
2
2
2
2
2
2
2
74LV595
LIMITS
–40 to +125 °C
– 24 –
– 24 –
– 24 –
– 18 –
– 18 –
– 5 –
– 5 –
– 20 –
UNIT
ns
ns
ns
MHz
1998 Apr 20
8
Page 9
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
AC WAVEFORMS
VM = 1.5V at VCC 2.7V
V
= 0.5 * VCC at V
M
and V
V
OL
output load.
V
X
V
X
V
Y
V
Y
OH
= V
+ 0.3V at VCC ≥ 2.7V
OL
= V
+ 0.1VCC at VCC < 2.7V
OL
= V
– 0.3V at VCC 2.7V
OH
= V
– 0.1VCC at VCC < 2.7V
OH
CP INPUT
GND
V
OH
Q
OUTPUT
n
V
OL
are the typical output voltage drop that occur with the
V
I
CC
2.7V
V
M
t
t
PHL
1/f
max
W
t
PLH
V
M
74LV595
V
I
OE INPUT
GND
V
CC
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
OL
V
OH
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
Figure 3. 3-State enable and disable times for input OE.
V
M
t
PLZ
t
PHZ
outputs
enabled
t
PZL
t
V
PZH
V
X
V
Y
outputs
disabled
M
V
M
outputs
enabled
SV00344
SV00718
Figure 1. Clock (SHCP) to output (Q7’), propagation delays, the
shift clock pulse width and the maximum shift clock frequency.
V
I
SHCP INPUT
GND
ST
INPUT
CP
GND
V
OUTPUT
Q
n
V
OH
OL
V
M
t
su
V
I
V
M
t
W
t
PLH
V
M
1/f
max
t
PHL
SV00727
Figure 2. Storage clock (STCP) to output (Qn) propagation
delays, the storage clock pulse width and the shift clock to
storage clock set-up time.
V
I
SHCP INPUT
GND
V
I
D
INPUT
S
GND
v
OH
’ OUTPUT V
Q
7
V
OL
V
M
t
su
t
h
V
M
M
t
su
t
h
SV00722
Figure 4. Data set-up and hold times for the data input (DS).
1998 Apr 20
9
Page 10
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
AC WAVEFORMS (Continued)
VM = 1.5V at VCC 2.7V
V
= 0.5 * VCC at V
M
and V
V
OL
output load.
V
X
V
X
V
Y
V
Y
OH
= V
+ 0.3V at VCC ≥ 2.7V
OL
= V
+ 0.1VCC at VCC < 2.7V
OL
= V
– 0.3V at VCC 2.7V
OH
= V
– 0.1VCC at VCC < 2.7V
OH
MR INPUT
SH
CP
Q7’ OUTPUT
are the typical output voltage drop that occur with the
GND
INPUT
GND
V
V
2.7V
CC
V
I
V
M
t
W
t
V
I
t
OH
OL
PHL
rem
V
M
V
M
TEST CIRCUIT
V
CC
PULSE
GENERATOR
V
I
D.U.T.
R
T
V
O
C
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitance
L
R
= Termination resistance should be equal to Z
T
SWITCH POSITION
TEST S
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 V
GND
1
CC
V
CC
< 2.7V V
Figure 6. Load circuitry for switching times.
74LV595
50pF
L
of pulse generators.
OUT
V
I
CC
2.7V2.7–3.6V
S
1
RL = 1k
RL = 1k
2 * V
Open
GND
SV00895
CC
SV00728
Figure 5. Master reset (MR) pulse width, the master reset to
output (Q
) propagation delay and the master reset to shift
7’
clock (SH
) removal time.
CP
1998 Apr 20
10
Page 11
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV595
1998 Apr 20
11
Page 12
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV595
1998 Apr 20
12
Page 13
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74LV595
1998 Apr 20
13
Page 14
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74LV595
1998 Apr 20
14
Page 15
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
NOTES
74LV595
1998 Apr 20
15
Page 16
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift register
with output latches (3-State)
DEFINITIONS
74LV595
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
print code Date of release: 05-96
Document order number: 9397-750-04455
All rights reserved. Printed in U.S.A.
1998 Apr 20
16
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