Page 1
INTEGRATED CIRCUITS
74LV574
Octal D-type flip-flop;
positive edge-trigger (3-State)
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Jun 10
Page 2
Philips Semiconductors Product specification
74L V574Octal D-type flip-flop; positive edge-trigger (3-State)
FEA TURES
•Wide operating voltage: 1.0 to 5.5V
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) 0.8V at VCC = 3.3V,
OLP
= 25°C
(output VOH undershoot) 2V at VCC = 3.3V,
OHV
= 25°C
= 2.7V and VCC = 3.6V
CC
•Common 3-State output enable input
•Output capability: bus driver
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
= input frequency in MHz; CL = output load capacity in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
(C
2. The condition is V
= 25°C; tr =tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Q
n
Maximum clock frequency CL = 15pF, VCC = 3.3V 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop Notes 1 and 2 25 pF
2
x fi (CL V
= GND to V
I
CC
2
fo) where:
CC
DESCRIPTION
The 74LV574 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT574.
The 74LV574 is an octal D-type flip–flop featuring separate D-type
inputs for each flip-flop and non-inverting 3-state outputs for bus
oriented applications. A clock (CP) and an output enable (OE
are common to all flip-flops.
The eight flip-flops will store the state of their individual D-inputs that
meet the set-up and hold times requirements on the LOW-to-HIGH
CP transition.
When OE
the outputs. When OE
impedance OFF-state. Operation of the OE
state of the flip-flops.
CL = 15pF
VCC = 3.3V
is LOW, the contents of the eight flip-flops is available at
is HIGH, the outputs go to the high
input does not affect the
13 ns
) input
ORDERING AND PACKAGE INFORMA TION
PACKAGES TEMPERATURE RANGE
20-Pin Plastic DIL –40°C to +125°C 74LV574 N 74LV574 N SOT146-1
20-Pin Plastic SO –40°C to +125°C 74LV574 D 74LV574 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C 74LV574 DB 74LV574 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV574 PW 74LV574PW DH SOT360-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enabled input (active LOW)
2, 3, 4, 5,
6, 7, 8, 9
19, 18, 17, 16,
15, 14, 13, 12
10 GND Ground (0V)
11 CP
20 VCC Positive supply voltage
D0–D7 Data inputs
Q0–Q7 3-State flip-flop outputs
Clock input (LOW-to-HIGH,
edge-triggered)
OUTSIDE NORTH
AMERICA
FUNCTION TABLE
OPERATING
Load and read
Load register and
disable outputsHH↑↑lh
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
Z = High impedance OFF-state
↑ = LOW–to–HIGH clock transition
NORTH AMERICA PKG. DWG. #
INPUTS
MODES
register
LOW-to-HIGH CP transition
OE CP Dn
LL↑↑l
FLIP-FLOPS
h
INTERNAL
L
H
L
H
OUTPUTS
Q0 to Q7
L
H
Z
Z
1998 Jun 10 853-1990 19545
2
Page 3
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
PIN CONFIGURATION
1
OE
D0
2
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
10
GND
LOGIC SYMBOL
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
CP
OE
LOGIC SYMBOL (IEEE/IEC)
20
19
18
17
16
15
14
13
12
11
SV00714
VCC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
11
1
2
3
4
5
6
7
8
9
EN
1D
C1
19
18
17
16
15
14
13
12
SV00716
FUNCTIONAL DIAGRAM
2
11
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1
19
18
17
16
15
14
13
12
SV00715
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
9
D7
11
CP
1
OE
FF1 to FF8
3–STATE
OUTPUTS
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
SV00717
19
18
17
16
15
14
13
12
1998 Jun 10
3
Page 4
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
LOGIC DIAGRAM
D0
D
D1 D2 D3 D4 D5 D6 D7
Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
CP
FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8
CP
OE
ABSOLUTE MAXIMUM RA TINGS
Q0
CP
CP
Q1 Q2 Q3 Q4 Q5 Q6 Q7
CP
CP
CP
CP
1, 2
CP
SV00342
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
P
TOT
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– bus driver outputs
DC VCC or GND current for types with
,
–bus driver outputs
Storage temperature range –65 to +150 °C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V 35 mA
70 mA
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
1
1.0 3.3 5.5 V
CC
CC
–40
–40
–
–
–
–
–
–
–
–
+85
+125
500
200
100
50
T
V
V
tr, t
CC
V
amb
DC supply voltage See Note
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free
air
Input rise and fall times
f
NOTES:
1. The LV is guaranteed to function down to V
1998 Jun 10
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
V
= 2.7V to 3.6V
CC
VCC = 3.6V to 5.5V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
4
V
V
°C
ns/V
Page 5
Philips Semiconductors Product specification
V
V
V
V
HIGH l
t
voltage all out uts
V
OH
V
voltage; BUS driver
LOW l
t
voltage all out uts
V
OL
V
voltage; BUS driver
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL PARAMETER TEST CONDITIONS
VCC = 1.2V 0.9 0.9
IH
HIGH level Input
voltage
VCC = 2.0V 1.4 1.4
VCC = 2.7 to 3.6V 2.0 2.0
VCC = 4.5 to 5.5V 0.7*V
VCC = 1.2V 0.3 0.3
IL
LOW level Input
voltage
VCC = 2.0V 0.6 0.6
VCC = 2.7 to 3.6V 0.8 0.8
VCC = 4.5 to 5.5 0.3*V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
evel outpu
;
VCC = 2.7V; VI = VIH or V
p
VCC = 3.0V; VI = VIH or V
VCC = 4.5V;VI = VIH or V
HIGH level output
VCC = 3.0V;VI = VIH or V
;
outputs
VCC = 4.5V;VI = VIH or V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
evel outpu
;
VCC = 2.7V; VI = VIH or V
p
VCC = 3.0V;VI = VIH or V
VCC = 4.5V;VI = VIH or V
LOW level output
VCC = 3.0V;VI = VIH or V
;
outputs
Input leakage
I
I
current
OZ
CC
3-State output
OFF-state current
Quiescent supply
current; MSI
I
I
VCC = 4.5V;VI = VIH or V
VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA
VCC = 5.5V; VI = VIH or V
VO = VCC or GND
VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
Additional
CC
quiescent supply
current per input
VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 100µA 4.3 4.5 4.3
–IO = 8mA 2.40 2.82 2.20
–IO = 16mA 3.60 4.20 3.50
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 8mA 0.20 0.40 0.50
IO = 16mA 0.35 0.55 0.65
-40°C to +85°C -40°C to +125°C
MIN TYP
CC
1
MAX MIN MAX
0.7*V
CC
CC
5 10 µA
0.3*V
UNIT
CC
1998 Jun 10
5
Page 6
Philips Semiconductors Product specification
P
CP to Qn
3 State out ut
OE
3 State out ut
OE
Clock
idth
HIGH or LOW
t
Figure 3
ns
t
Figure 3
ns
Maxi
k
ulse frequency
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
t
PHL/tPLH
PARAMETER WAVEFORM
ropagation delay
Figure 1, 4
3-State output
t
PZH/tPZL
enable time
to Qn
Figure 2, 4
3-State output
t
PHZ/tPLZ
t
W
su
h
f
max
disable time
to Qn
pulse w
Set-up time
Dn to CP
Hold time
Dn to CP
mum cloc
p
Figure 2, 4
Figure 1
Figure 1
NOTE:
1. Unless otherwise stated, all typical values are at T
2. Typical value measured at V
CC
= 3.3V.
amb
CONDITION
LIMITS
–40 to +85 °C
VCC(V) MIN TYP MAX MIN MAX
1.2 – 80 – – –
2.0 – 27 34 – 43
2.7 – 20 25 – 31
3.0 to 3.6 – 15
2
20 – 25
4.5 to 5.5 – – 17 – 21
1.2 – 70 – – –
2.0 – 24 34 – 43
2.7 – 18 25 – 31
3.0 to 3.6 – 13
2
20 – 25
4.5 to 5.5 – – 17 – 21
1.2 – 75 – – –
2.0 – 27 27 – 34
2.7 – 21 21 – 26
3.0 to 3.6 – 16
2
17 – 21
4.5 to 5.5 – – 15 – 18
2.0 34 9 – 41 –
2.7 25 6 – 30 –
3.0 to 3.6 20 5
2
– 24 –
1.2 – 10 – – –
2.0 22 4 – 26 –
2.7 16 3 – 19 –
3.0 to 3.6 13 2
2
– 15 –
1.2 – –10 – – –
2.0 5 –4 – 5 –
2.7 5 –3 – 5 –
3.0 to 3.6 5 –2
2
– 5 –
2.0 15 40 – 12 –
2.7 19 58 – 16 –
3.0 to 3.6 24 70
2
– 20 –
= 25°C.
LIMITS
–40 to +125 °C
UNIT
ns
ns
ns
ns
MHz
1998 Jun 10
6
Page 7
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
AC WAVEFORMS
VM = 1.5V at VCC 2.7V and 3.6V
V
= 0.5 * VCC at V
M
and V
V
OL
output load.
V
X
V
X
V
Y
V
Y
OH
= V
+ 0.3V at VCC 2.7V and 3.6V
OL
= V
+ 0.1VCC at VCC < 2.7V and 4.5V
OL
= V
– 0.3V at VCC 2.7V and 3.6V
OH
= V
– 0.1VCC at VCC < 2.7V and 4.5V
OH
CP INPUT
GND
V
OH
Q
OUTPUT
n
V
OL
V
I
2.7V and 4.5V
CC
are the typical output voltage drop that occur with the
1/f
max
V
M
t
W
t
PHL
V
M
t
PLH
SV00718
Figure 1. Clock (CP) to output (Qn) propagation delays, the
clock pulse (CP) and the maximum clock pulse frequency
Figure 3. Data set-up and hold times for the Dn input to the CP
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
V
I
CP INPUT
GND
V
I
INPUT
D
n
GND
V
OH
Q
OUTPUT V
n
V
OL
NOTE: the shaded areas indicate when the input is permitted to change
for predictable output performance.
(1)
V
M
t
su
t
h
V
M
M
input
t
su
t
h
SV00345
OE INPUT
GND
V
OUTPUT
LOW-to-OFF
OFF-to-LOW
V
V
OUTPUT
HIGH-to-OFF
OFF-to-HIGH
GND
V
I
V
M
t
CC
OL
OH
PLZ
t
PHZ
outputs
enabled
V
X
V
Y
outputs
disabled
t
PZL
t
PZH
Figure 2. 3-state enable and disable times
V
M
V
outputs
enabled
SV00344
TEST CIRCUIT
V
CC
PULSE
GENERATOR
V
I
D.U.T.
R
T
V
O
50 pF
C
L
Test Circuit for Outputs
M
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitiance.
L
RT = Termination resistance should be equal to Z
OUT
of pulse generators.
SWITCH POSITION
TEST
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 * V
GND
S
1
CC
V
CC
< 2.7V V
2.7–3.6V
4.5V
V
2.7V
V
I
CC
CC
Figure 4. Load circuitry for switching times
2 * V
Open
GND
R
= 1k
L
R
= 1k
L
SV00896
CC
1998 Jun 10
7
Page 8
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
1998 Jun 10
8
Page 9
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1998 Jun 10
9
Page 10
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
1998 Jun 10
10
Page 11
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
1998 Jun 10
11
Page 12
Philips Semiconductors Product specification
74LV574Octal D-type flip-flop; positive edge-trigger (3-State)
DEFINITIONS
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04454
1998 Jun 10
12
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