Page 1
INTEGRATED CIRCUITS
74LV377
Octal D-type flip-flop with data enable;
positive edge-trigger
Product specification
Supersedes data of 1997 Mar 04
IC24 Data Handbook
1998 Jun 10
Page 2
Philips Semiconductors Product specification
OPERATING MODES
Octal D-type flip-flop with data enable;
positive edge-trigger
FEA TURES
•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) 0.8V @ VCC = 3.3V,
OLP
= 25°C
(output VOH undershoot) 2V @ VCC = 3.3V,
OHV
= 25°C
•Ideal for addressable register applications
•Data enable for address and data synchronization applications
•Eight positive-edge triggered D-type flip-flops
•Output capability: standard
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
2. The condition is V
= 25°C; tr = tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
Propagation delay
CP to Q
n
Maximum clock frequency
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop Notes 1 and 2 20 pF
2
fi (CL V
= GND to V
I
= 2.7V and VCC = 3.6V
CC
PARAMETER CONDITIONS TYPICAL UNIT
CL = 15pF
VCC = 3.3V
2
fo) where:
CC
CC
74L V377
DESCRIPTION
The 74LV377 is a low–voltage CMOS device and is pin and function
compatible with 74HC/HCT377.
The 74LV377 has eight edge-triggered, D-type flip-flops with
individual D inputs and Q outputs. A common clock (CP) input loads
all flip-flops simultaneously when the data enable (E
state of each D input, one set-up time before the LOW-to-HIGH
clock transition, is transferred to the corresponding output (Q
the flip-flop. The E
the LOW-to-HIGH transition for predictable operation.
input must be stable only one set-up time prior to
13 ns
77 MHz
) is LOW. The
) of
n
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
20-Pin Plastic DIL –40°C to +125°C 74LV377 N 74LV377 N SOT146-1
20-Pin Plastic SO –40°C to +125°C 74LV377 D 74LV377 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +125°C 74LV377 DB 74LV377 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +125°C 74LV377 PW 74LV377PW DH SOT360-1
PIN DESCRIPTION
PIN
NUMBER
1 E Data enable input (active-LOW)
2, 5, 6, 9, 12,
15, 16, 19
3, 4, 7, 8, 13,
14, 17, 18
10 GND Ground (0V)
11 CP
20 V
SYMBOL FUNCTION
Q0 to Q
D0 to D
CC
flip-flop outputs
7
Data inputs
7
Clock input
(LOW-to-HIGH, edge-triggered)
Positive supply voltage
FUNCTION TABLE
INPUTS OUTPUTS
CP E D
Load ‘‘1’’ ↑ l h H
Load ‘‘0’’ ↑ l l L
Hold (do nothing)
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
↑ = LOW–to–HIGH CP transition
X = Don’t care
↑
X
H
n
h
X
No change
X
No change
Q
n
1998 Jun 10 853–1935 19545
2
Page 3
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
PIN CONFIGURATION
GND
1
E
2
Q
0
3
D
0
4
D
1
5
Q
1
6
Q
2
7
D
2
8
D
3
9
Q
3
10
20
V
CC
19
Q
7
18
D
7
17
D
6
16
Q
6
15
Q
5
14
D
5
13
D
4
Q
12
4
11
CP
LOGIC SYMBOL (IEEE/IEC)
11
1
3
4
7
8
13
14
17
18
1C2
G1
2D
74LV377
2
5
6
9
12
15
16
19
LOGIC SYMBOL
3
4
89
13
17 16
18
SV00667
SV00669
FUNCTIONAL DIAGRAM
11
CP
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
E
2
5
67
12
1514
19
1
SV00668
D
D
D
D
D
D
D
D
E
CP
0
1
2
3
4
5
6
7
FF1
FF8
to
OUTPUTS
3
4
7
8
13
14
17
18
1
11
Q
0
2
Q
1
5
Q
2
6
Q
3
9
Q
4
12
Q
5
15
Q
6
16
Q
7
19
SV00670
1998 Jun 10
3
Page 4
Philips Semiconductors Product specification
P
mW
Octal D-type flip-flop with data enable;
positive edge-trigger
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
V
CC
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
±I
±I
±I
DC supply voltage See Note 1 1.0 3.3 3.6 V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times
f
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
V
= 2.7V to 3.6V
CC
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
–40
–40
–
–
–
–
–
–
–
1, 2
PARAMETER CONDITIONS RATING UNIT
DC supply voltage –0.5 to +4.6 V
CC
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
IK
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
OK
DC output source or sink current
O
– standard outputs
–0.5V < VO < VCC + 0.5V 25 mA
74LV377
CC
CC
+85
+125
500
200
100
V
V
°C
ns/V
±I
GND
±I
T
stg
DC VCC or GND current for types with
,
–standard outputs
CC
Storage temperature range –65 to +150 °C
50 mA
Power dissipation per package for temperature range: –40 to +125°C
–plastic DIL above +70°C derate linearly with 12mW/K 750
tot
–plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
–plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Jun 10
4
Page 5
Philips Semiconductors Product specification
voltage
voltage
Octal D-type flip-flop with data enable;
positive edge-trigger
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. V oltages are referenced to GND (ground = 0V).
SYMBOL PARAMETER TEST CONDITIONS
VCC = 1.2V 0.9 0.9
IH
HIGH level Input
V
VCC = 2.0V 1.4 1.4
VCC = 2.7 to 3.6V 2.0 2.0
VCC = 1.2V 0.3 0.3
IL
LOW level Input
V
VCC = 2.0V 0.6 0.6
VCC = 2.7 to 3.6V 0.8 0.8
VCC = 1.2V; VI = VIH or V
HIGH level output
voltage; all outputs
V
OH
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
IL;
IL;
IL;
IL;
HIGH level output
voltage;
STANDARD
VCC = 3.0V; VI = VIH or V
IL;
outputs
VCC = 1.2V; VI = VIH or V
LOW level output
voltage; all outputs
V
OL
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
IL;
IL;
IL;
IL;
LOW level output
voltage;
STANDARD
VCC = 3.0V; VI = VIH or V
IL;
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; MSI
I
VCC = 3.6V; VI = VCC or GND 1.0 1.0 µA
VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 160 µA
Additional
CC
quiescent supply
current per input
VCC = 2.7V to 3.6V; VI = VCC – 0.6V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 6mA 2.40 2.82 2.20
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 6mA 0.25 0.40 0.50
-40°C to +85°C -40°C to +125°C
MIN TYP
LIMITS
1
MAX MIN MAX
74LV377
UNIT
V
V
V
V
1998 Jun 10
5
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Philips Semiconductors Product specification
CONDITION
t
gy
Figure 1
ns
HIGH or LOW
t
Figure 2
ns
t
Figure 2
ns
t
Figure 2
ns
t
Figure 2
ns
ulse frequency
Octal D-type flip-flop with data enable;
positive edge-trigger
AC CHARACTERISTICS
CC
L
= 3.3V.
=1KW
Figure 2
Figure 1
amb
= 25°C.
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; R
SYMBOL PARAMETER WAVEFORM
PHL/tPLH
t
W
su
su
h
h
f
max
Propagation delay
CP to Q
n
Clock pulse width
Set-up time
Dn to CP
Set-up time
E to CP
Hold time
Dn to CP
Hold time
E to CP
Maximum clock
p
NOTES:
1. Unless otherwise stated, all typical values are at T
2. Typical value measured at V
74LV377
LIMITS
–40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP1MAX MIN MAX
1.2 – 80 – – –
2.0 – 27 51 – 61
2.7 – 20 38 – 45
3.0 to 3.6 – 15
2.0 34 9 – 41 –
2.7 25 6 – 30 –
3.0 to 3.6 20 5
1.2 – 25 – – –
2.0 22 9 – 26 –
2.7 16 6 – 19 –
3.0 to 3.6 13 5
1.2 – 10 – – –
2.0 22 4 – 26 –
2.7 16 3 – 19 –
3.0 to 3.6 13 2
1.2 – –15 – – –
2.0 5 –5 – 5 –
2.7 5 –4 – 5 –
3.0 to 3.6 5 –3
1.2 – –5 – – –
2.0 5 –2 – 5 –
2.7 5 –2 – 5 –
3.0 to 3.6 5 –1
2.0 14 40 – 12 –
2.7 19 58 – 16 –
3.0 to 3.6 24 70
2
30 – 36
2
2
2
2
2
2
– 24 –
– 15 –
– 15 –
– 5 –
– 5 –
– 20 –
UNIT
ns
MHz
1998 Jun 10
6
Page 7
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
AC WAVEFORMS
VM = 1.5V at VCC 2.7V
V
= 0.5V * VCC at V
M
VOL and V
output load.
Qn OUTPUT
OH
V
CP INPUT
GND
V
V
are the typical output voltage drop that occur with the
CC
OH
OL
Figure 1. Clock (CP) to output (Qn) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
V
CC
E INPUT
GND
V
CC
INPUT
D
n
GND
V
CC
CP INPUT
GND
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
CC
V
V
M
2.7V
M
t
W
t
PHL
t
su
STABLE
V
M
t
su
1/f
max
t
PLH
V
M
SV00707
t
h
t
h
V
M
t
h
t
su
tW
SV00671
TEST CIRCUIT
V
V
PULSE
GENERATOR
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitance
L
RT = Termination resistance should be equal to Z
TEST
t
PLH/tPHL
Figure 3. Load circuitry for switching times
I
D.U.T.
R
T
Test Circuit for switching times
V
CC
< 2.7V V
2.7–3.6V 2.7V
CC
74LV377
V
O
50pF
C
L
of pulse generators.
OUT
V
I
CC
RL = 1k
SV00901
Figure 2. Data set-up and hold times from the data input (Dn)
and from the enable input (E
) to the clock (CP).
1998 Jun 10
7
Page 8
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1
74LV377
1998 Jun 10
8
Page 9
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74LV377
1998 Jun 10
9
Page 10
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
74LV377
1998 Jun 10
10
Page 11
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
74LV377
1998 Jun 10
11
Page 12
Philips Semiconductors Product specification
Octal D-type flip-flop with data enable;
positive edge-trigger
DEFINITIONS
74LV377
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
print code Date of release: 05-96
Document order number: 9397-750-04449
All rights reserved. Printed in U.S.A.
1998 Jun 10
12
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