Datasheet 74LV373PW, 74LV373N, 74LV373D Datasheet (Philips)

INTEGRATED CIRCUITS

74LV373

Octal D-type transparent latch (3-State)

Product specification Supersedes data of 1997 March 04 IC24 Data Handbook

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1998 Jun 10

Philips Semiconductors Product specification

74L V373Octal D-type transparent latch (3-State)

FEA TURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0V to 3.6V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce) < 0.8V at V

OLP

= 25°C

(output VOH undershoot) > 2V at V

OHV

= 25°C

= 2.7V and V

CC

•Common 3-State output enable input

•Output capability: bus driver

•I

category: MSI

CC

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1. C

PD

P

= CPD  V

D

= input frequency in MHz; CL = output load capacity in pF;

f

i

f

= output frequency in MHz; VCC = supply voltage in V;

o

 (C

2. The condition is V

= 25°C; tr = tf 2.5 ns

amb

CC

2

 V

L

 fo) = sum of the outputs.

CC

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay D

to Q

n

LE to Q

n

Input capacitance 3.5 pF Power dissipation capacitance per latch Notes 1, 2 22 pF

2

x fi  (CL  V

= GND to V

I

CC.

2

 fo) where:

CC

= 3.6V

CC

= 3.3V ,

DESCRIPTION

The 74LV373 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT373.

The 74LV373 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE input are common to all internal latches.

The ‘373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE available at the outputs. When OE high impedance OFF-state. Operation of the OE affect the state of the latches.

The ‘373’ is functionally identical to the ‘573’, but the ‘573’ has a different pin arrangement.

CL = 15pF VCC = 3.3V 10

is LOW, the contents of the eight latches are

is HIGH, the outputs go to the

input does not

12

)

ns

ORDERING AND PACKAGE INFORMA TION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

20-Pin Plastic DIL –40°C to +125°C 74LV373 N 74LV373 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV373 D 74LV373 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV373 DB 74LV373 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +125°C 74L V373 PW 74LV373PW DH SOT360-1

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE Output enabled input (active LOW)

2, 5, 6, 9, 12,

15, 16, 19

3, 4, 7, 8, 13,

14, 17, 18

10 GND Ground (0V) 11 LE Latch enable input (active HIGH) 20 V

1998 Jun 10 853–1934 19545

Q0–Q73-State latch outputs

D0–D

CC

Data inputs

7

Positive supply voltage

2

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

PIN CONFIGURATION

1

OE

2

Q

0

3

D

0

4

D

1

5

Q

1

6

Q

2

7

D

2

8

D

3

9

Q

3

10

GND

LOGIC SYMBOL (IEEE/IEC)

11

1

3

4

7

8

13

14

17

18

C1 EN1

1D

20

V

19

Q

18

D

17

D

16

Q

15

Q

14

D

13

D Q

12

11

LE

SV00657

LOGIC SYMBOL

CC

7

6

5

4

3

D

4

D

7

D

8

D

13

D

14

D

17

D

18

D

11

LE

OE

Q

0

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

0

1

2

3

4

5

6

7

1

2 5 6

9 12 15 16 19

SV00658

FUNCTIONAL DIAGRAM

3

D

0

4

D

1

7

D

2

5

6

9

12

2

8

D

3

13

D

4

D

14

5

D

17

6

D

18

7

LATCH 1 to 8

3–STATE OUTPUTS

15

LE

16

19

11

1

OE

2

Q

0

5

Q

1

6

Q

2

9

Q

3

12

Q

4

15

Q

5

16

Q

6

19

Q

7

LOGIC DIAGRAM

D

0

LE

OE

1998 Jun 10

D LATCH

1

LE

SV00659

D

1

Q

D LATCH

2 LE

Q0

D

2

Q

LE

D LATCH

3 LE

Q1

D

3

Q

LE

D LATCH

4 LE

Q2

D

4

Q

LE

D LATCH

5 LE

Q3

D

5

Q

LE

D LATCH

6 LE

Q4

D

6

Q

LE

D LATCH

7 LE

Q5

D

7

Q

LE

Q6

D LATCH

8 LE

SV00660

Q

LE

Q7

SV00661

3

Philips Semiconductors Product specification

OPERATING MODES

P

mW

74LV373Octal D-type transparent latch (3-State)

FUNCTION TABLE

Enable and read register (transparent mode)

Latch and read register

Latch register and disable outputs

INPUTS

OE LE Dn

L L

H H

H

L L

L

I

h

I

h

INTERNAL

LATCHES

L

H

L

H

L

H

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = Don’t care Z = High impedance OFF-state

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

V

CC

V

T

amb

tr, t

NOTE:

1. The LV is guaranteed to function down to V

DC supply voltage See Note1 1.0 3.3 5.5 V Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free air

Input rise and fall times

f

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

CC

See DC and AC characteristics

VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V V

= 3.6V to 5.5V

CC

–40 –40

– – – –

OUTPUTS

Q0 to Q

L

H

L

H

Z Z

CC CC

+85

+125

500 200 100

50

7

V V

°C

ns/V

ABSOLUTE MAXIMUM RATINGS

1, 2

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

SYMBOL

V

CC

±I

IK

±I

OK

±I

O

±I

GND

±I

CC

T

stg

DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current

– bus driver outputs DC VCC or GND current for types with

,

–bus driver outputs Storage temperature range –65 to +150 °C

PARAMETER CONDITIONS RATING UNIT

–0.5V < VO < VCC + 0.5V 35 mA

70 mA

Power dissipation per package for temperature range: –40 to +125°C –plastic DIL above +70°C derate linearly with 12mW/K 750

tot

–plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500 –plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Jun 10

4

Philips Semiconductors Product specification

V

voltage all out uts

V

OH

V

voltage; BUS driver

voltage all out uts

V

OL

V

voltage; BUS driver

74LV373Octal D-type transparent latch (3-State)

DC CHARACTERISTICS

Over recommended operating conditions. V oltages are referenced to GND (ground = 0V).

LIMITS

SYMBOL PARAMETER TEST CONDITIONS

VCC = 1.2V 0.9 0.9

IH

HIGH level Input voltage

VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*V VCC = 1.2V 0.3 0.3

IL

LOW level Input voltage

VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 4.5 to 5.5 0.3*V VCC = 1.2V; VI = VIH or V VCC = 2.0V; VI = VIH or V

HIGH level output

;

V

VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or V VCC = 4.5V; VI = VIH or V

HIGH level output

;

outputs

VCC = 3.0V; VI = VIH or V VCC = 4.5V; VI = VIH or V

VCC = 1.2V; VI = VIH or V VCC = 2.0V; VI = VIH or V

LOW level output

;

V

VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or V VCC = 4.5V; VI = VIH or V

LOW level output

;

outputs Input leakage

I

current

OZ

CC

3-State output OFF-state current

Quiescent supply current; MSI

I

VCC = 3.0V; VI = VIH or V VCC = 4.5V; VI = VIH or V

VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA VCC = 5.5V; VI = VIH or V

VO = VCC or GND VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA

IL; IL; IL; IL; IL;

IL;

IL; IL;

IL; IL; IL; IL;

IL;

Additional

CC

quiescent supply current per input

VCC = 2.7V to 3.6V; VI = VCC – 0.6V 500 850 µA

∆I

NOTE:

1. All typical values are measured at T

amb

= 25°C.

–IO = 100µA 1.2 –IO = 100µA 1.8 2.0 1.8 –IO = 100µA 2.5 2.7 2.5 –IO = 100µA 2.8 3.0 2.8 –IO = 100µA 4.3 4.5 4.3

–IO = 8mA 2.40 2.82 2.20 –IO = 16mA 3.60 4.20 3.50

IO = 100µA 0 IO = 100µA 0 0.2 0.2 IO = 100µA 0 0.2 0.2 IO = 100µA 0 0.2 0.2 IO = 100µA 0 0.2 0.2

IO = 8mA 0.20 0.40 0.50 IO = 16mA 0.35 0.55 0.65

-40°C to +85°C -40°C to +125°C

MIN TYP

CC

1

MAX MIN MAX

0.7*V

CC

5 10 µA

0.3*V

UNIT

CC

V

1998 Jun 10

5

Philips Semiconductors Product specification

CONDITION

D

n

Q

n

LE to Q

n

3-State out ut

OE

Q

3-State out ut

OE

Q

tsuSetup time D

LE

Figure 4

ns

thHold time D

LE

Figure 4

ns

74LV373Octal D-type transparent latch (3-State)

AC CHARACTERISTICS

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = K

LIMITS

SYMBOL PARAMETER WAVEFORM

t

PHL/tPLH

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

W

Propagation delay

to

Propagation delay

-

p

enable time

to

n

-

p

disable time

to

n

Figure 1, 5

Figure 2, 5

Figure 3

LE pulse width HIGH Figure 2

p

n

to

NOTES:

CC CC

= 25°C

amb

= 3.3V = 5.0V

1. All typical values are measured at T

2. Typical values are measured at V

3. Typical values are measured at V

–40 to +85 °C –40 to +125 °C

VCC(V) MIN TYP1MAX MIN MAX

1.2 – 65 – – –

2.0 – 22 37 – 48

2.7 – 16 28 – 35

3.0 to 3.6 – 13

2

22 – 28

4.5 to 5.5 – – 16 – 20

1.2 – 80 – – –

2.0 – 27 43 – 54

2.7 – 20 26 – 33

3.0 to 3.6 – 15

4.5 to 5.5 – 9.5

2

25 – 31

3

19 – 24

1.2 – 80 – – –

2.0 – 27 46 – 58

2.7 – 20 28 – 35

3.0 to 3.6 – 15

2

27 – 34

4.5 to 5.5 – – 23 – 29

1.2 – 75 – – –

2.0 – 27 46 – 58

2.7 – 21 28 – 35

3.0 to 3.6 – 16

2

27 – 34

4.5 to 5.5 – – 23 – 29

2.0 34 10 – 41 –

2.7 25 8 – 30 –

3.0 to 3.6 20 6

2

– 24 –

1.2 – 25 – – –

2.0 17 9 – 20 –

2.7 13 6 – 15 –

3.0 to 3.6 10 5

2

– 12 –

1.2 – –15 – – –

2.0 5 –5 – 5 –

2.7 5 –3 – 5 –

3.0 to 3.6 5 –3

2

– 5 –

UNIT

ns

1998 Jun 10

6

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

AC WAVEFORMS

VM = 1.5V at VCC  2.7V and  3.6V V

= 0.5V * VCC at V

M

and V

V

OL

output load. V

X

V

X

V

Y

V

Y

OH

= V

+ 0.3V at V

OL

= V

+ 0.1VCC at VCC < 2.7V and  4.5V

OL

= V

– 0.3V at VCC  2.7V and  3.6V

OH

= V

– 0.1VCC at VCC < 2.7V and  4.5V

OH

V

Dn INPUT

GND

V

OH

Q

OUTPUT

n

V

OL

are the typical output voltage drop that occur with the

I

 2.7V and  4.5V

CC

 2.7V and  3.6V

CC

V

t

PHL

M

t

PLH

V

M

SV00662

Figure 1. Data input (Dn) to output (Qn) propagation delays and

the output transition times.

V

I

LE INPUT

GND

V

Qn OUTPUT

V

OH

OL

V

M

t

W

t

PHL

V

M

t

PLH

SV00663

Figure 2. Latch enable input (LE) pulse width, the latch enable

input to output (Q

) propagation delays

n

and the output transition times.

V

I

OE INPUT

GND

V

CC

OUTPUT

Q

n

LOW-to-OFF OFF-to-LOW

V

OL

V

OH

OUTPUT

Q

n

HIGH-to-OFF OFF-to-HIGH

GND

V

M

t

PLZ

t

PHZ

outputs

enabled

t

PZL

V

t

PZH

M

V

M

outputs enabled

SV00664

V

X

V

Y

outputs

disabled

Figure 3. 3-State enable and disable times.

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

TEST CIRCUIT

V

I

Dn INPUT

GND

LE INPUT

GND

V

I

V

M

t

h

t

su

V

M

Figure 4. Data set-up and hold times

PULSE

GENERATOR

for the D

input to the LE input.

n

V

CC

V

I

D.U.T.

R

T

V

Test Circuit for Outputs

DEFINITIONS

RL = Load resistor

= Load capacitance includes jig and probe capacitiance.

C

L

RT = Termination resistance should be equal to Z

SWITCH POSITION

TEST

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 * V

GND

S

1

CC

V

CC

< 2.7V V

2.7–3.6V

 4.5V

Figure 5. Load circuitry for switching times

O

50 pF

C

L

of pulse generators.

OUT

V

I

CC

2.7V V

CC

t

h

t

su

SV00665

2 * V

CC

Open GND

R

= 1k

L

R

= 1k

L

SV00896

1998 Jun 10

7

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1998 Jun 10

8

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1998 Jun 10

9

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

1998 Jun 10

10

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

1998 Jun 10

11

Philips Semiconductors Product specification

74LV373Octal D-type transparent latch (3-State)

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-04447

 

1998 Jun 10

12