Datasheet 74LV174PW, 74LV174N, 74LV174DB, 74LV174D Datasheet (Philips)

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Page 1

INTEGRATED CIRCUITS

74LV174

Hex D-type flip-flop with reset; positive-edge trigger

Product specification Supersedes data of 1997 Apr 07 IC24 Data Handbook

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1998 May 20

Page 2

Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

FEA TURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between V

•Typical V

amb

•Typical V

amb

(output ground bounce)  0.8V @ VCC = 3.3V,

OLP

= 25°C

(output VOH undershoot)  2V @ VCC = 3.3V,

OHV

= 25°C

= 2.7V and VCC = 3.6V

•Output capability: standard

•I

category: MSI

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

PHL/tPLH

max

NOTES:

1. C

is used to determine the dynamic power dissipation (PD in µW)

= CPD  V

= input frequency in MHz; CL = output load capacitance in pF;

= output frequency in MHz; VCC = supply voltage in V;

 (C

2. The condition is V

= 25°C; tr = tf 2.5 ns

amb

 V

 fo) = sum of the outputs.

PARAMETER CONDITIONS TYPICAL UNIT

Propagation delay CP to Q

MR to Q

Maximum clock frequency 77 MHz Input capacitance 3.5 pF

Power dissipation capacitance per flip-flop

x fi  (CL  V

= GND to V

 fo) where:

DESCRIPTION

The 74LV174 is a low–voltage Si–gate CMOS device and is pin and function compatible with the 74HC/HCT174.

The 74LV174 has six edge–triggered D–type flip–flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip–flops simultaneously .

The register is fully edge–triggered. The state of each D input, one set–up time prior to the LOW–to–HIGH clock transition, is transferred to the corresponding output of the flip–flop.

A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs.

The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements.

CL = 15pF VCC = 3.3V

VCC = 3.3V Notes 1 and 2

74L V174

16 13

17 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

16-Pin Plastic DIL –40°C to +125°C 74LV174 N 74LV174 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV174 D 74LV174 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV174 DB 74LV174 DB SOT338-1 16-Pin Plastic TSSOP –40°C to +125°C 74LV174 PW 74LV174PW DH SOT403-1

1998 May 20 853–1964 19422

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Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

PIN CONFIGURATION

107

98GND CP

SV00347

LOGIC SYMBOL

74LV174

SV00348

PIN DESCRIPTION

NUMBER

1 MR 2, 5, 7, 10,

12, 15 3, 4, 6, 11,

13, 14 8 GND Ground (0V)

9 CP 16 V

SYMBOL FUNCTION

Asynchronous master reset (active LOW)

Q0 to Q

D0 to D

Flip-flop outputs

Data inputs

Clock input (LOW-to-HIGH, edgetriggered)

Positive supply voltage

LOGIC SYMBOL (IEEE/IEC)

9 1

SV00349

1998 May 20

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Philips Semiconductors Product specification

OPERATING MODES

Hex D-type flip-flop with reset; positive edge-trigger

FUNCTIONAL DIAGRAM

11 10

13 12

14 15

FF1 FF6

FUNCTION TABLE

Reset (clear) L X X L

Load ‘1’ H ↑ h H Load ‘0’ H ↑ l L

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the

L = LOW voltage level l = LOW voltage level one set-up time prior to the

q = Lower case letter indicates the state of referenced input ↑ = LOW–to–HIGH clock transition

74LV174

INPUTS OUTPUTS

MR CP D

LOW-to-HIGH CP transition

LOW-to-HIGH CP transition one set-up time prior to the LOW-to-HIGH CP transition

SV00350

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

amb

tr, t

NOTES:

1. The LV is guaranteed to function down to V

DC supply voltage See Note1 1.0 3.3 5.5 V Input voltage 0 – V

Output voltage 0 – V

Operating ambient temperature range in free air

Input rise and fall times

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

See DC and AC characteristics

VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V

–40 –40

– – –

– – – –

CC CC

+85

+125

500 200 100

V V

°C

ns/V

1998 May 20

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Philips Semiconductors Product specification

HIGH l

voltage all out uts

LOW l

voltage all out uts

Hex D-type flip-flop with reset; positive edge-trigger

ABSOLUTE MAXIMUM RATINGS

1, 2

74LV174

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

±I

GND

±I

stg

TOT

PARAMETER CONDITIONS RATING UNIT

DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA DC output source or sink current

– standard outputs DC VCC or GND current for types with

–standard outputs

–0.5V < VO < VCC + 0.5V 25 mA

50 mA

Storage temperature range –65 to +150 °C Power dissipation per package

–plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP)

for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K

750 500 400

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

DC CHARACTERISTICS FOR THE LV FAMILY

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

SYMBOL P ARAMETER TEST CONDITIONS

MIN TYP

VCC = 1.2V 0.9 0.9

HIGH level Input voltage

LOW level Input voltage

evel outpu

;

HIGH level output voltage; STANDARD outputs

evel outpu

;

LOW level output voltage; STANDARD outputs

VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*V

VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 4.5 to 5.5 0.3*V VCC = 1.2V; VI = VIH or V VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

VCC = 3.0V; VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V VCC = 1.2V; VI = VIH or V

VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

VCC = 3.0V;VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V

–IO = 100µA 1.2

IL;

–IO = 100µA 1.8 2.0 1.8

IL;

–IO = 100µA 2.5 2.7 2.5

IL;

–IO = 100µA 2.8 3.0 2.8

IL;

–IO = 100µA 4.3 4.5 4.3

IL;

–IO = 6mA 2.40 2.82 2.20

IL;

–IO = 12mA 3.60 4.20 3.50

IL;

IO = 100µA 0

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 6mA 0.25 0.40 0.50

IL;

IO = 12mA 0.35 0.55 0.65

IL;

LIMITS

-40°C to +85°C -40°C to +125°C

MAX MIN MAX

0.7*V

0.3*V

UNIT

1998 May 20

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Philips Semiconductors Product specification

SYMBOL

PARAMETER

TEST CONDITIONS

UNIT

CP to Q

MR to Q

Figure 1

Figure 2

MR to CP

Set

Hex D-type flip-flop with reset; positive edge-trigger

DC CHARACTERISTICS FOR THE LV FAMILY (Continued)

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

Input leakage

current

Quiescent supply current; MSI

Additional

quiescent supply current per input

∆I

NOTE:

1. All typical values are measured at T

AC CHARACTERISTICS

GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ

SYMBOL

PHL/tPLH

PHL

rem

PARAMETER WAVEFORM

ropagation delay

Clock pulse width HIGH to LOW

Master reset pulse width LOW

emoval time

-up time

VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA

VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA

VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA

= 25°C.

amb

CONDITION

VCC(V) MIN TYP1MAX MIN MAX

1.2 – 100 – – –

2.0 – 34 43 – 53

Figure 1

2.7 – 25 31 – 39

3.0 to 3.6 – 19

4.5 to 5.5 – 13

1.2 – 80 – – –

2.0 – 27 43 – 53

Figure 2

2.7 – 20 31 – 39

3.0 to 3.6 – 15

4.5 to 5.5 – 11

2.0 34 10 – 41 –

2.7 25 8 – 30 –

3.0 to 3.6 20 6

4.5 to 5.5 13 4

2.0 34 9 – 41 –

2.7 25 6 – 30 –

3.0 to 3.6 20 5 – 24 –

4.5 to 5.5 13 4

1.2 – –20 – – –

2.0 5 –7 – 5 –

Figure 2

2.7 5 –5 – 5 –

3.0 to 3.6 5 –4

4.5 to 5.5 5 –3

1.2 – 10 – – –

2.0 22 4 – 26 –

Figure 3

2.7 16 3 – 19 –

3.0 to 3.6 13 2

4.5 to 5.5 9 1

74LV174

LIMITS

-40°C to +85°C -40°C to +125°C

LIMITS

–40 to +85 °C

2 3

25 – 31 21 – 26

– 24 –

– 5 –

– 15 –

LIMITS

–40 to +125 °C

UNIT

1998 May 20

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Philips Semiconductors Product specification

Hold ti

Figure 1

MHz

Hex D-type flip-flop with reset; positive edge-trigger

AC CHARACTERISTICS (Continued)

GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 1KΩ

SYMBOL

max

PARAMETER WAVEFORM

Figure 3

Maximum clock pulse frequency

NOTES:

1. Unless otherwise stated, all typical values are at T

2. Typical value measured at V

3. Typical value measured at V

= 3.3V.

= 5.0V.

AC WAVEFORMS

VM = 1.5V at VCC  2.7V  3.6V V

= 0.5V * VCC at V

and V

output load.

are the typical output voltage drop that occur with the

 2.7V and  4.5V

amb

CONDITION

VCC(V) MIN TYP1MAX MIN MAX

1.2 – –10 – – –

2.0 5 –4 – 5 –

2.7 5 –2 – 5 –

3.0 to 3.6 5 –2

4.5 to 5.5 5 –1

2.0 14 40 – 12 –

2.7 19 58 – 16 –

3.0 to 3.6 24 70

4.5 to 5.5 36 100

= 25°C.

LIMITS

–40 to +85 °C

2 3

74LV174

LIMITS

–40 to +125 °C

– 5 –

– 20 –

UNIT

1/f

max

CP INPUT

GND

Qn OUTPUT

PHL

PLH

SV00351

Figure 1. The clock (CP) to output (Qn) propagation delays, the

clock pulse width, and the maximum clock pulse frequency.

MR INPUT

GND

CP INPUT

GND

Qn OUTPUT

PHL

rem

SV00352

Figure 2. The master reset (MR) pulse width, the master reset to output (Q

) propagation delay and the master reset to clock

removal time.

1998 May 20

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Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

AC WAVEFORMS (Continued)

VM = 1.5V at VCC  2.7V  3.6V V

= 0.5V * VCC at V

and V

output load.

CP INPUT

OUTPUT V

GND

INPUT

GND

are the typical output voltage drop that occur with the

 2.7V and  4.5V

TEST CIRCUIT

PULSE

GENERATOR

DEFINITIONS

RL = Load resistor CL = Load capacitance includes jig and probe capacitiance RT = Termination resistance should be equal to Z

TEST

PLH/tPHL

74LV174

2.7V

50pF

of pulse generators.

OUT

SV00902

D.U.T.

Test Circuit for Outputs

< 2.7V

2.7–3.6V ≥ 4.5 V V

Figure 4. Load circuitry for switching times

RL= 1k

SV00353

Figure 3. Data set-up and hold times for the data input (D

n).

NOTE:

The shaded areas indicate when the input is permitted to change for predictable output performance.

1998 May 20

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Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74LV174

1998 May 20

Page 10

Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74LV174

1998 May 20

Page 11

Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

74LV174

1998 May 20

Page 12

Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

74LV174

1998 May 20

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Philips Semiconductors Product specification

Hex D-type flip-flop with reset; positive edge-trigger

NOTES

74LV174

1998 May 20

Page 14

Philips Semiconductors Product specification

74LV174Hex D-type flip-flop with reset; positive edge-trigger

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1998

print code Date of release: 05-96 Document order number: 9397-750-04433

 

1997 Apr 07