Page 1
INTEGRATED CIRCUITS
74LV165
8-bit parallel-in/serial-out shift register
Product specification
Supersedes data of 1997 May 15
IC24 Data Handbook
1998 May 07
Page 2
Philips Semiconductors Product specification
74L V1658-bit parallel-in/serial-out shift register
FEA TURES
•Wide operating voltage: 1.0 to 5.5 V
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
•Asynchronous 8-bit parallel load
•Synchronous serial input
•Output capability: standard
•I
category: MSI
CC
CC
CC
= 3.6 V
CC
= 3.3 V,
= 3.3 V,
DESCRIPTION
The 74LV165 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT165.
The 74LV165 is an 8-bit parallel-load or serial-in shift register with
complementary serial outputs (Q
stage. When the parallel load (PL
D
to D7 inputs are loaded into the register asynchronously. When PL
0
is HIGH, data enters the register serially at the DS input and shifts one
place to the right (Q
transition. This feature allows parallel-to-serial converter expansion by
tying the Q
7
0→Q1→Q2
output to the DS input of the succeeding stage.
The clock input is a gated-OR structure which allows one input to be
used as an active LOW clock enable (CE
for the CP and CE
inputs is arbitrary and can be reversed for layout
convenience. The LOW-to-HIGH transition of input CE
take place while CP HIGH for predictable operation. Either the CP or
the CE
should be HIGH before the LOW-to-HIGH transition of PL to
prevent shifting the data when PL
and Q7) available from the last
7
) input is LOW, parallel data from the
, etc.) with each positive-going clock
) input. The pin assignment
should only
is activated.
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr = t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
CE, CP to Q7, Q
PL to Q7, Q
D7 to Q7, Q
f
C
C
max
I
PD
Maximum clock frequency 78 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per gate
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD × V
D
f
= input frequency in MHz; CL = output load capacitance in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
× V
L
2
× fi (CL × V
CC
2
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
CL = 15 pF;
7
7
7
2
× fo) where:
CC
VCC = 3.3 V
V
= 3.3 V
CC
VI = GND to V
CC
1
18
18
14
35 pF
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV165 N 74LV165 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV165 D 74LV165 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV165 DB 74LV165 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV165 PW 74LV165PW DH SOT403-1
PIN CONFIGURATION
1
PL
2
CP
3
D
4
4
D
5
5
D
6
6
D
7
7
Q
7
8
GND
1998 May 07 853–1915 19349
16
15
14
13
12
11
10
9
SV00585
V
CE
D
D
D
D
D
Q
CC
3
2
1
0
S
7
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1
2 CP
7 Q
8 GND Ground (0 V)
9 Q
10 D
11, 12, 13, 14, 3, 4, 5, 6 D0 to D7Parallel data inputs
15 CE
16 V
2
PL Asynchronous parallel load
input (active LOW)
Clock input (LOW to
HIGH, edge-triggered)
7
7
S
Complementary output from
the last stage
Serial output from last stage
Serial data input
Clock enable input
(active LOW)
CC
Positive supply voltage
Page 3
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
LOGIC SYMBOL
10
D
S
D
11
0
12
D
1
13
D
2
14
D
3
3
D
4
4
D
5
5
D
6
6
D
7
1
PL
CP
215
LOGIC SYMBOL (IEEE/IEC)
1
15
2
10
11
12
13
14
3
4
5
6
SRG8
C2 [LOAD]
G1 [SHIFT]
>
1
1
3D
2D
2D
C3/
CE
Q
7
Q
7
SV00586
9
7
9
7
SV00587
FUNCTIONAL DIAGRAM
D
1
PL
D
10
15
S
2
CP
CE
D2D
0
1
8–BIT SHIFT REGISTER
PARALLEL– IN / SERIAL – OUT
74LV165
654314131211
D
D
3
D6D
D
5
4
7
9
Q
7
7
Q
7
SV00588
LOGIC DIAGRAM
D
S
CP
CE
PL
1998 May 07
D
0
S
D
Q
D
CP
FF0 FF1 FF2 FF3 FF4 FF5 FF6 FF7
R
D
D
1
S
D
Q
D
CP
R
D
D
2
S
D
Q
D
CP
R
D
D
3
S
D
Q
D
CP
R
D
D
4
S
D
Q
D
CP
R
D
D
5
S
D
Q
D
CP
R
D
D
6
S
D
Q
D
CP
R
D
3
D
7
S
D
D
CP
R
D
Q
Q
Q
7
Q
7
SV00589
Page 4
Philips Semiconductors Product specification
OPERATING MODES
Parallel load
Serial Shift
8-bit parallel-in/serial-out shift register
74LV165
FUNCTION TABLE
INPUTS Qn REGISTERS OUTPUTS
PL CE CP D
S
D0–D
7
Q
0
Q1–Q
6
Q
7
L X X X L L L–L L H
L X X X H H H–H H L
H L ↑ l X L q0–q
H L ↑ h X H q0–q
Hold “do nothing” H H X X X q
5
5
0
q1–q
6
q
6
q
6
q
7
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
V
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 5.5 V
CC
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times
f
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
–40
–40
–
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
50
ns/V
Q
q
q
q
°C
7
6
6
7
V
V
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0 V).
SYMBOL
V
I
I
I
I
I
T
P
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 07
CC
IK
OK
O
GND
CC
stg
TOT
1, 2
PARAMETER CONDITIONS RATING UNIT
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
DC VCC or GND current for types with
,
– standard outputs 50
–0.5V < VO < VCC + 0.5V
25
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
4
mA
mA
mW
Page 5
Philips Semiconductors Product specification
V
V
V
V
voltage all out uts
g
V
g
V
voltage all out uts
g
V
g
V
8-bit parallel-in/serial-out shift register
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
SYMBOL P ARAMETER TEST CONDITIONS
VCC = 1.2 V 0.9 0.9
IH
HIGH level Input
voltage
VCC = 2.0 V 1.4 1.4
VCC = 2.7 to 3.6 V 2.0 2.0
VCC = 4.5 to 5.5 V 0.7V
VCC = 1.2 V 0.3 0.3
IL
LOW level Input
voltage
VCC = 2.0 V 0.6 0.6
VCC = 2.7 to 3.6 V 0.8 0.8
VCC = 4.5 to 5.5 0.3V
VCC = 1.2 V; VI = VIH or V
VCC = 2.0 V; VI = VIH or V
OH
HIGH level output
;
V
VCC = 2.7 V; VI = VIH or V
p
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
OH
HIGH level output
volta
e;
STANDARD
outputs
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
VCC = 1.2 V; VI = VIH or V
VCC = 2.0 V; VI = VIH or V
OL
LOW level output
;
V
VCC = 2.7 V; VI = VIH or V
p
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
LOW level output
volta
OL
e;
STANDARD
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; MSI
I
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
VCC = 5.5 V; VI = VCC or GND 1.0 1.0 µA
VCC = 5.5 V; VI = VCC or GND; IO = 0 20.0 160 µA
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
Additional
CC
quiescent supply
current per input
VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 100µA 4.3 4.5 4.3
–IO = 6mA 2.40 2.82 2.20
–IO = 12mA 3.60 4.20 3.50
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 6mA 0.25 0.40 0.50
IO = 12mA 0.35 0.55 0.65
-40°C to +85°C -40°C to +125°C
MIN TYP
CC
LIMITS
1
MAX MIN MAX
0.7V
CC
74LV165
CC
0.3V
UNIT
CC
V
V
1998 May 07
5
Page 6
Philips Semiconductors Product specification
CONDITION
CE, CP to Q7, Q
7
PL to Q7, Q
7
D
7
Q7, Q
7
t
Figures 1, 2
ns
t
Figures 1, 2
ns
PL to CP, CE
D
S
CP, CE
CE to CP CP to CE
8-bit parallel-in/serial-out shift register
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL PARAMETER WAVEFORM
t
PLH/tPHL
t
PLH/tPHL
t
PLH/tPHL
w
w
t
rem
t
su
t
su
Propagation delay
CE, CP to Q, Q
Propagation delay
PL to Q, Q
Propagation delay
to
D
to Q, Q
Clock Pulse width
HIGH or LOW
Parallel load pulse
width LOW
Removal time
PL to CP, CE
Set-up time
to
D
to CP, CE
Set-up time
CE to CP; CP to CE
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
Figures 1, 2
74LV165
LIMITS
–40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP
1.2 – 115 –
2.0 – 38 61 – 76
2.7 – 27 43 – 54
3.0 to 3.6 – 22
4.5 to 5.5 – 15 24 – 30
1.2 – 110 –
2.0 – 35 56 – 70
2.7 – 24 39 – 49
3.0 to 3.6 – 20
4.5 to 5.5 – 14 22 – 27
1.2 – 90 –
2.0 – 28 45 – 56
2.7 – 20 32 – 40
3.0 to 3.6 – 17
4.5 to 5.5 – 11 18 – 22
2.0 34 10 – 41 –
2.7 25 8 – 30 –
3.0 to 3.6 20 7
4.5 to 5.5 15 5 – 18 –
2.0 34 10 – 41 –
2.7 25 8 – 30 –
3.0 to 3.6 20 7
4.5 to 5.5 15 5 – 18 –
1.2 – 40 – – –
2.0 24 15 – 30 –
2.7 18 11 – 23 –
3.0 to 3.6 17 10
4.5 to 5.5 12 7 – 15 –
1.2 – –8 – – –
2.0 22 –2 – 26 –
2.7 16 –1 – 19 –
3.0 to 3.6 13 –1
4.5 to 5.5 9 0 – 10 –
1.2 – 20 – – –
2.0 22 7 – 26 –
2.7 16 5 – 19 –
3.0 to 3.6 13 4
4.5 to 5.5 9 3 – 10 –
1
MAX MIN MAX
2
36 – 45
2
33 – 41
2
27 – 33
2
2
2
– 24 –
– 24 –
2
– 21 –
2
– 15 –
– 15 –
UNIT
ns
ns
ns
ns
ns
ns
1998 May 07
6
Page 7
Philips Semiconductors Product specification
SYMBOL
PARAMETER
WAVEFORM
UNIT
D
n
PL
Hold time
D
PL
Hold time
CP
CE
f
Figures 1, 2
MH
8-bit parallel-in/serial-out shift register
AC CHARACTERISTICS (
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
t
su
t
h
t
h
max
NOTES:
1. Unless otherwise stated, all typical values are measured at T
2. Typical values are measured at V
Set-up time
to
D
to PL
Ds to CP, CE
to
n
CE to CP,
to
Maximum clock
pulse frequency
Continued
Figures 1, 2
Figures 1, 2
Figures 1, 2
= 3.3 V.
CC
)
74LV165
CONDITION –40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP
1.2 – 25 – – –
2.0 22 8 – 26 –
2.7 16 6 – 19 –
3.0 to 3.6 13 5
4.5 to 5.5 9 4 – 10 –
1.2 – 20 – – –
2.0 22 7 – 26 –
2.7 16 5 – 19 –
3.0 to 3.6 13 4 – 15 –
4.5 to 5.5 9 3 – 10 –
1.2 – –30 – – –
2.0 5 –8 – 5 –
2.7 5 –6 – 5 –
3.0 to 3.6 5 –5
4.5 to 5.5 5 –4 – 5 –
2.0 14 40 – 12 –
2.7 19 60 – 16 –
3.0 to 3.6 24 65
4.5 to 5.5 36 75 – 30 –
= 25°C
amb
1
MAX MIN MAX
2
– 15 –
2
– 5 –
2
– 20 –
ns
ns
ns
z
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V .
= 0.5 × VCC at VCC < 2.7 V;
V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
1/f
V
I
CP INPUT
GND
V
OH
Q7 or Q
7
OUTPUT
V
OL
The changing to output assumes internal Q6 opposite state from Q7.
V
M
t
PHL
Figure 1. Clock (CP) to output (Q7 or Q7) propagation delays,
the clock pulse width and the maximum clock frequency.
Note to Figures 1 and 2
The changing to output assumes internal Q
max
t
W
V
M
t
PLH
SV00590
opposite state from Q7.
6
V
I
PL INPUT
GND
V
I
CE
, CP INPUT
GND
V
OH
Q7 or Q7 OUTPUT
V
OL
The changing to output assumes internal Q6 opposite state from Q7.
V
M
t
t
W
PHL
t
rem
V
M
V
M
SV00591
Figure 2. Parallel load (PL) pulse width, the parallel load to
output (Q
or Q7) propagation delays, the parallel load to clock
7
(CP) and clock enable (CE
) removal time.
1998 May 07
7
Page 8
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V .
= 0.5 × VCC at VCC < 2.7 V;
V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
V
I
D
INPUT
7
GND
V
OH
Q7 OUTPUT
V
OL
V
OH
OUTPUT
Q
7
V
OL
Figure 3. Data input (Dn) to output (Q7 or Q7) propagation
V
M
t
PLH
V
M
t
PHL
V
M
delays when PL
t
PHL
t
PLH
is LOW.
SV00592
74LV165
V
I
Dn INPUT
GND
V
INPUT
PL
GND
Figure 5. Set-up and hold times from the data inputs (Dn)
TEST CIRCUIT
PULSE
GENERATOR
V
M
t
su
t
I
H
V
M
to the parallel load input (PL
V
cc
V
l
D.U.T.
R
T
t
su
t
H
SV00593
).
V
O
50pF
C
L
RL= 1k
V
CP, CE
INPUT
GND
V
D
INPUT
S
GND
V
CP, CE
INPUT
GND
CE may change only from HIGH-to-LOW while CP is LOW. The shaded
areas indicate when the input is permitted to change for predictable output
performance.
see note
I
V
M
t
h
tsu(L)
t
V
M
t
su
stable
h
t
h
V
M
I
I
tsu(H)
t
W
SV00595
Figure 4. Set-up an d ho l d t i m e s fr o m t he s e r i a l da t a i nput (DS) to
the clock (CP) and the clock enable (CE
enable input (CE
) to the clock input (CP) and from the clock input
(CP) to the clock enable input (CE
) inputs, from the clock
).
Note to Figure 4
may change only from HIGH-to-LOW while CP is LOW. The
CE
shaded areas indicate when the input is permitted to change for
predictable output performance.
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
RT = Termination resistance should be equal to Z
TEST
t
PLH/tPHL
V
CC
< 2.7V
2.7–3.6V
≥ 4.5 V V
V
V
2.7V
CC
CC
OUT
I
Figure 6. Load circuitry for switching times.
of pulse generators.
SV00902
1998 May 07
8
Page 9
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV165
1998 May 07
9
Page 10
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV165
1998 May 07
10
Page 11
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74LV165
1998 May 07
11
Page 12
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74LV165
1998 May 07
12
Page 13
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
74LV165
NOTES
1998 May 07
13
Page 14
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register
DEFINITIONS
74LV165
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code Date of release: 05-96
Document order number: 9397-750-04432
1998 May 07
14
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