•Optimized for Low Voltage applications: 1.0 to 3.6V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) 0.8V @ VCC = 3.3V,
OLP
= 25°C
(output VOH undershoot) 2V @ VCC = 3.3V,
OHV
= 25°C
= 2.7V and VCC = 3.6V
CC
•Gated serial data inputs
•Asynchronous master reset
•Output capability: standard
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacitance in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
2. The condition is V
= 25°C; tr =tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETERCONDITIONSTYPICALUNIT
Propagation delay
CP to Q
n
MR to Q
n
Maximum clock frequency78MHz
Input capacitance3.5pF
Power dissipation capacitance per gate
2
x fi (CL V
= GND to V
I
CC
2
fo) where:
CC
DESCRIPTION
The 74LV164 is a low-voltage Si-gate CMOS device and is pin and
function compatible with the 74HC/HCT164.
The 74LV164 is an 8-bit edge-triggered shift register with serial data
entry and an output from each of the eight stages. Data is entered
serially through one of two inputs (D
used as an active HIGH enable for data entry through the other
input. Both inputs must be connected together or an unused input
must be tied HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of
the clock (CP) input and enters into Q
the two data inputs (D
the rising clock edge.
A LOW on the master reset (MR) input overrides all other inputs and
clears the register asynchronously, forcing all outputs LOW.
CL = 15pF
VCC = 3.3V
VCC = 3.3V
Notes 1 and 2
, Dsb) that existed one set-up time prior to
sa
or Dsb); either input can be
sa
, which is the logical AND of
0
12
12
40pF
ns
ORDERING INFORMATION
PACKAGESTEMPERATURE RANGE OUTSIDE NORTH AMERICANORTH AMERICAPKG. DWG. #
14-Pin Plastic DIL–40°C to +125°C74LV164 N74LV164 NSOT27-1
14-Pin Plastic SO–40°C to +125°C74LV164 D74LV164 DSOT108-1
14-Pin Plastic SSOP Type II–40°C to +125°C74LV164 DB74LV164 DBSOT337-1
14-Pin Plastic TSSOP Type I–40°C to +125°C74L V164 PW74LV164PW DHSOT402-1
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
±I
OK
±I
DC supply voltage–0.5 to +7.0V
DC input diode currentVI < –0.5 or VI > VCC + 0.5V20mA
IK
DC output diode currentVO < –0.5 or VO > VCC + 0.5V50mA
DC output source or sink current
O
– standard outputs
8-BIT SERIAL-IN/PARALLEL-OUT
SHIFT REGISTER
Q
Q
0
3
1Q2Q3
5
4
Q
4Q5Q6Q7
6
10
1112
13
SV00384
1, 2
PARAMETERCONDITIONSRATINGUNIT
–0.5V < VO < VCC + 0.5V
74LV164
FUNCTION TABLE
OPERATING
MODES
Reset (clear)LXxxLL – L
Shift
H= HIGH voltage level
h= HIGH voltage level one set-up time prior to the
LOW-to-HIGH CP transition
L= LOW voltage level
l= LOW voltage level one set-up time prior to the
LOW-to-HIGH CP transition
q= Lower case letter indicates the state of referenced input
one set-up time prior to the LOW-to-HIGH CP transition
↑= LOW-to-HIGH clock transition
INPUTSOUTPUTS
MRCPDsaD
H
↑
H
↑
H
↑
H
↑
sbQ0
l
l
l
h
h
l
h
h
25
Q1 – Q
L
q0 – q
q0 – q
L
q0 – q
L
q0 – q
H
mA
7
6
6
6
6
±I
GND
±I
CC
T
stg
P
TOT
DC VCC or GND current for types with
,
–standard outputs
50
Storage temperature range–65 to +150°C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mA
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOLPARAMETERCONDITIONSMINTYP.MAXUNIT
V
CC
V
V
T
amb
tr, t
NOTES:
1. The LV is guaranteed to function down to V
DC supply voltageSee Note 11.03.35.5V
Input voltage0–V
I
Output voltage0–V
O
Operating ambient temperature range in free
air
Input rise and fall times
f
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
–40
–40
–
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
50
V
V
°C
ns/V
1998 May 07
4
Page 5
Philips SemiconductorsProduct specification
V
V
V
V
HIGH l
t
voltage all out uts
V
g
V
LOW l
t
voltage all out uts
V
g
V
8-bit serial-in/parallel-out shift register
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
SYMBOLP ARAMETERTEST CONDITIONS
MINTYP
VCC = 1.2V0.90.9
HIGH level Input
IH
voltage
LOW level Input
IL
voltage
V
OH
evel outpu
;
HIGH level output
voltage;
OH
STANDARD
outputs
V
OL
evel outpu
;
LOW level output
voltage;
OL
STANDARD
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; MSI
I
Additional
CC
quiescent supply
current per input
∆I
NOTES:
1. All typical values are measured at T
VCC = 2.0V1.41.4
VCC = 2.7 to 3.6V2.02.0
VCC = 4.5 to 5.5V0.7*V
CC
VCC = 1.2V0.30.3
VCC = 2.0V0.60.6
VCC = 2.7 to 3.6V0.80.8
VCC = 4.5 to 5.50.3*V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
p
VCC = 3.0V; VI = VIH or V
VCC = 4.5V;VI = VIH or V
VCC = 3.0V;VI = VIH or V
VCC = 4.5V;VI = VIH or V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
p
VCC = 3.0V;VI = VIH or V
VCC = 4.5V;VI = VIH or V
VCC = 3.0V;VI = VIH or V
VCC = 4.5V;VI = VIH or V
–IO = 100µA1.2
IL;
–IO = 100µA1.82.01.8
IL;
–IO = 100µA2.52.72.5
IL;
–IO = 100µA2.83.02.8
IL;
–IO = 100µA4.34.54.3
IL;
–IO = 6mA2.402.822.20
IL;
–IO = 12mA3.604.203.50
IL;
IO = 100µA0
IL;
IO = 100µA00.20.2
IL;
IO = 100µA00.20.2
IL;
IO = 100µA00.20.2
IL;
IO = 100µA00.20.2
IL;
IO = 6mA0.250.400.50
IL;
IO = 12mA0.350.550.65
IL;
VCC = 5.5V; VI = VCC or GND1.01.0µA
VCC = 5.5V; VI = VCC or GND; IO = 020.0160µA
VCC = 2.7V to 3.6V; VI = VCC –0.6V500850µA
= 25°C.
amb
74LV164
LIMITS
-40°C to +85°C -40°C to +125°C
1
MAXMINMAX
0.7*V
CC
CC
0.3*V
UNIT
CC
V
V
1998 May 07
5
Page 6
Philips SemiconductorsProduct specification
P
CP to Q
n
P
MR to Q
n
t
Figure 1
ns
t
Figure 2
ns
R
MR to CP
Set
D
sa
D
sb
CP
Hold ti
D
sa
D
sb
CP
f
Figure 1
MHz
8-bit serial-in/parallel-out shift register
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL
t
PHL/tPLH
t
PHL
W
W
t
rem
t
su
t
h
max
NOTE:
1. Unless otherwise stated, all typical values are at T
2. Typical value measured at V
3. Typical value measured at V
PARAMETERWAVEFORM
ropagation delay
ropagation delay
Figure 1
Figure 2
Clock pulse width
HIGH to LOW
Master reset pulse
width; LOW
emoval time
-up time
,
to
me
,
to
Figure 2
Figure 3
Figure 3
Maximum clock
pulse frequency
= 3.3V.
CC
= 5.0V.
CC
amb
= 25°C.
CONDITION
LIMITS
–40 to +85 °C
LIMITS
–40 to +125 °C
VCC(V)MINTYP1MAXMINMAX
1.2–75–––
2.0–2639–49
2.7–1929–36
3.0 to 3.6–14
4.5 to 5.5–12
2
23–29
2
19–24
1.2–75–––
2.0–2639–49
2.7–1929–36
3.0 to 3.6–14
4.5 to 5.5–12
2
23–29
2
19–24
2.0349–41–
2.7256–30–
3.0 to 3.6205
4.5 to 5.5134
2
2
–24–
16
2.03410–41–
2.7258–30–
3.0 to 3.6206
4.5 to 5.5135
2
2
–24–
16
1.2–30–––
2.01910–24–
2.7148–18–
3.0 to 3.6116
4.5 to 5.585
2
2
–14–
10
1.2–15–––
2.0225–26–
2.7164–19–
3.0 to 3.6133
4.5 to 5.592
2
2
–15–
10
1.2––10–––
2.05–3–5–
2.75–2–5–
3.0 to 3.65–2
4.5 to 5.55–1
2
2
–5–
5
2.01440–12–
2.71958–16–
3.0 to 3.62470
4.5 to 5.536100
2
2
–20–
30
74LV164
UNIT
ns
ns
ns
ns
ns
1998 May 07
6
Page 7
Philips SemiconductorsProduct specification
8-bit serial-in/parallel-out shift register
AC WAVEFORMS
VM = 1.5V at VCC 2.7V 3.6V
V
= 0.5V * VCC at V
M
and V
V
OL
output load.
CP INPUT
Qn OUTPUT
are the typical output voltage drop that occur with the
OH
V
I
GND
V
OH
V
OL
Figure 1. The clock (CP) to output (Qn) propagation delays, the
clock pulse width, the output transition times and the
2.7V and 4.5V
CC
1/f
max
V
M
t
w
t
PHL
V
M
maximum clock pulse frequency
t
PLH
SV00351
74LV164
V
l
CP INPUT
GND
V
l
INPUT
D
n
GND
V
OH
Q
OUTPUTV
n
V
OL
Figure 3. Data set-up and hold times for the Dn inputs
NOTE:
The shaded areas indicate when the input is permitted to change for
predictable output performance.
TEST CIRCUIT
V
M
t
su
t
h
V
M
M
V
cc
t
su
t
h
SV00353
Vi
MR INPUT
GND
CP INPUT
GND
V
Qn OUTPUT
V
Vi
OH
OL
V
M
t
t
PHL
w
V
M
t
rem
V
M
SV00352
Figure 2. The master reset (MR) pulse width, the master reset to
output (Q
) propagation delay and the master reset to clock
n
(CP) removal time
V
O
C
PULSE
GENERATOR
V
l
D.U.T.
R
T
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
RT = Termination resistance should be equal to Z
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print codeDate of release: 05-96
Document order number:9397-750-04431
1998 May 07
12
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