Page 1
INTEGRATED CIRCUITS
74LV109
Dual JK
flip-flop with set and reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Jun 06
IC24 Data Handbook
1998 Apr 20
Page 2
Philips Semiconductors Product specification
74L V109Dual JK flip-flop with set and reset; positive-edge trigger
FEA TURES
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
CC
CC
CC
= 3.3 V,
= 3.3 V,
•Output capability: standard
•I
category: flip-flops
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr =t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
nCP to nQ, nQ
nSD to nQ, nQ
nRD to nQ, nQ
f
max
C
C
I
PD
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop VI = GND to V
NOTE:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD × V
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
Σ (C
× V
L
2
× fi Σ (CL × V
CC
2
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
2
× fo) where:
CC
= 3.6 V
CL = 15 pF;
VCC = 3.3 V
DESCRIPTION
The 74LV109 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT109.
The 74LV109 is a dual positive-edge triggered JK
featuring individual J, K
) inputs; also complementary Q and Q outputs.
(R
D
inputs, clock (CP) inputs, set (SD) and reset
The set and reset are asynchronous active LOW inputs and operate
independently of the clock input.
The J and K
inputs control the state changes of the flip-flops as
described in the mode select function table. The J and K
be stable one set-up time prior to the LOW-to-HIGH clock transition
for predictable operation.
The JK
design allows operation as a D-type flip-flop by tying the
J and K
inputs together.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
14
12
12
CC
1
20 pF
-type flip-flop
inputs must
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV109 N 74LV109 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV109 D 74LV109 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV109 DB 74LV109 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV109 PW 74LV109PW DH SOT403-1
PIN CONFIGURATION
1R
1
D
2
1J
3
1K
4
1CP
1S
5
D
6
1Q
7
1Q
GND
1998 Apr 20 853-1986 19255
16
15
14
13
12
11
10
98
SV00517
V
2R
2J
2K
2CP
2S
2Q
2Q
CC
D
D
PIN DESCRIPTION
PIN
NUMBER
1, 15 1RD, 2R
2, 14, 3, 13
4, 12 1CP, 2CP
5, 11 1S
6, 10 1Q, 2Q True flip-flop outputs
7, 9 1Q, 2Q Complement flip-flop outputs
8 GND Ground (0 V)
16 V
2
SYMBOL FUNCTION
Asynchronous reset input
D
(active LOW)
1J, 2J,
1K, 2K
Synchronous inputs; flip-flops 1 and 2
Clock input (LOW-to-HIGH,
edge-triggered)
Asynchronous set inputs
2S
D,
D
(active LOW)
CC
Positive supply voltage
Page 3
Philips Semiconductors Product specification
Dual JK
flip-flop with set and reset; positive-edge trigger
LOGIC SYMBOL (IEEE/IEC)
5
S
2
1J
4
C1
3
1K
1
R
(a) (b)
610
79
LOGIC SYMBOL
11
5
1S
2S
D
74LV109
FUNCTIONAL DIAGRAM
11
S
14
1J
12
13
15
D
C1
1K
R
SV00519
5
1S
D
S
D
1J
2
1CP
4
1K
3
1R
D
1
11
2S
D
2J
14
2CP
12
2K
13
2R
15
D
J
CP
K
J
K
CP
R
S
R
Q
FF1
Q
D
D
Q
FF2
Q
D
1Q
1Q
2Q
10
2Q
SV00520
6
7
9
14 2J
4 1CP
12 2CP
13 2K
LOGIC DIAGRAM
2 1J
3 1K
J
CP
K
CP
1Q 6
Q
2Q 10
7
1Q
Q
2Q
9
2R
1R
D
D
15
1
SV00518
C
K
J
S
R
C
C
C
C
C
C
C
C
Q
Q
1998 Apr 20
C
SV00521
3
Page 4
Philips Semiconductors Product specification
OPERATING MODES
Dual JK
flip-flop with set and reset; positive-edge trigger
74LV109
FUNCTION TABLE
INPUTS OUTPUTS
nS
D
nR
D
nCP nJ nK nQ nQ
Asynchronous set L H X X X H L
Asynchronous reset H L X X X L H
Undetermined L L X X X H H
Toggle H H ↑ h l q q
Load “0” (reset) H H ↑ l l L H
Load “1” (set) H H ↑ h h H L
Hold “no change” H H ↑ l h q q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP transition.
X = don’t care
↑ = LOW-to-HIGH CP transition
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 3.6 V
CC
V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times except for
f
Schmitt-trigger inputs
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
-40
-40
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
ns/V
V
V
°C
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
"I
IK
"I
OK
"I
O
"I
GND
"I
CC
T
stg
P
TOT
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
DC VCC or GND current for types with
,
– standard outputs 50
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V
25
mA
mA
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW
NOTE:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 Apr 20
4
Page 5
Philips Semiconductors Product specification
voltage
voltage
V
V
V
V
CONDITION
t
gy
Figure 1
ns
t
gy
Figure 2
ns
Dual JK
flip-flop with set and reset; positive-edge trigger
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
SYMBOL P ARAMETER TEST CONDITIONS
VCC = 1.2 V 0.9 0.9
IH
HIGH level Input
V
VCC = 2.0 V 1.4 1.4
VCC = 2.7 to 3.6 V 2.0 2.0
VCC = 1.2 V 0.3 0.3
IL
LOW level Input
V
VCC = 2.0 V 0.6 0.6
VCC = 2.7 to 3.6 V 0.8 0.8
HIGH level output
OH
voltage; all outputs
VCC = 1.2 V; VI = VIH or V
VCC = 2.0 V; VI = VIH or V
VCC = 2.7 V; VI = VIH or V
VCC = 3.0 V; VI = VIH or V
IL;
IL;
IL;
IL;
HIGH level output
OH
voltage;
STANDARD
VCC = 3.0 V; VI = VIH or V
IL;
V
outputs
LOW level output
OL
voltage; all outputs
VCC = 1.2 V; VI = VIH or V
VCC = 2.0 V; VI = VIH or V
VCC = 2.7 V; VI = VIH or V
VCC = 3.0 V; VI = VIH or V
IL;
IL;
IL;
IL;
LOW level output
OL
voltage;
STANDARD
VCC = 3.0 V; VI = VIH or V
IL;
V
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; flip-flops
I
VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA
VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 80 µA
Additional
CC
quiescent supply
current per input
VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 6mA 2.40 2.82 2.20 V
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 6mA 0.25 0.40 0.50 V
-40°C to +85°C -40°C to +125°C
MIN TYP
LIMITS
1
MAX MIN MAX
74LV109
UNIT
V
V
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL PARAMETER WAVEFORM
PHL/tPLH
PLH
1998 Apr 20
Propagation delay
nCP to nQ, nQ
Propagation delay
nSD to nQ
LIMITS
–40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP1MAX MIN MAX
1.2 90
2.0 31 58 70
2.7 23 43 51
3.0 to 3.6 18
2
34 41
1.2 55
2.0 19 36 44
2.7 14 26 33
3.0 to 3.6 10
2
21 26
5
UNIT
Page 6
Philips Semiconductors Product specification
CONDITION
t
gy
Figure 2
ns
t
gy
Figure 2
ns
t
gy
Figure 2
ns
Clock
idth
HIGH or LOW
Set
width HIGH or LOW
t
Figure 2
ns
t
Figure 1
ns
t
Figure 1
ns
Maxi
k
ulse frequency
Dual JK
flip-flop with set and reset; positive-edge trigger
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL PARAMETER WAVEFORM
PHL
PHL
PLH
t
W
t
W
rem
su
h
f
max
NOTES:
1. Unless otherwise stated, all typical values are measured at T
2. Typical values are measured at V
Propagation delay
nSD to nQ
Propagation delay
nRD to nQ
Propagation delay
nRD to nQ
pulse w
or reset pulse
Removal time
nS
nRD to nCP
D,
Set-up time
nJ, nK to CP
Hold time
nJ, nK to nCP
mum cloc
p
= 3.3 V.
CC
Figure 1
Figure 2
Figure 1
LIMITS
–40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP1MAX MIN MAX
1.2 75
2.0 26 46 60
2.7 19 36 44
3.0 to 3.6 17
2
29 35
1.2 75
2.0 26 46 60
2.7 19 36 44
3.0 to 3.6 15
2
29 35
1.2 70
2.0 24 44 54
2.7 18 33 40
3.0 to 3.6 13
2
26 32
2.0 34 12 41
2.7 25 9 30
3.0 to 3.6 20 7
2
24
2.0 34 9 41
2.7 25 6 30
3.0 to 3.6 20 5
2
24
1.2 35
2.0 24 12 29
2.7 18 9 21
3.0 to 3.6 14 7
2
17
1.2 30
2.0 22 10 26
2.7 16 8 19
3.0 to 3.6 13 6
2
15
1.2 –5
2.0 5 –2 5
2.7 5 –1 5
3.0 to 3.6 5 0
2
5
2.0 14 40 12
2.7 19 58 16
3.0 to 3.6 24 70
= 25°C
amb
2
20
74LV109
UNIT
ns
ns
MHz
1998 Apr 20
6
Page 7
Philips Semiconductors Product specification
Dual JK
flip-flop with set and reset; positive-edge trigger
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
= 0.5 × VCC at VCC < 2.7 V;
V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
V
I
nJ, nK
INPUT
GND
nCP
INPUT
GND
V
OH
nQ
OUTPUT
V
OL
V
OH
nQ
OUTPUT
V
OL
The shaded areas indicate when the input is permitted to change
for predictable output performance.
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the nJ and nK
nJ, nK
hold times and the maximum clock pulse frequency.
V
M
t
su
t
h
V
I
V
t
t
M
PHL
PLH
1/f
max
t
W
V
M
V
M
t
su
t
h
t
PLH
t
PHL
SV00522
to nCP set-up, the nCP to
TEST CIRCUIT
V
V
PULSE
GENERATOR
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitance
L
RT = Termination resistance should be equal to Z
TEST
t
PLH/tPHL
Figure 3. Load circuitry for switching times.
I
D.U.T.
R
T
Test Circuit for switching times
V
CC
< 2.7V V
2.7–3.6V 2.7V
CC
74LV109
V
O
50pF
C
L
of pulse generators.
OUT
V
I
CC
RL = 1k
SV00901
V
l
nCP
INPUT
GND
nS
INPUT
GND
nR
INPUT
GND
V
OUTPUT
V
V
OUTPUT
V
OH
nQ
OH
nQ
V
l
D
V
M
t
t
V
l
D
OL
OL
W
t
PLH
V
M
t
PHL
V
M
rem
t
W
V
M
t
PHL
t
PLH
V
M
t
rem
SV00523
Figure 2. Set (nSD) and reset (nRD) input to output (nQ, nQ)
propagation delays, the set and reset pulse widths and the nR
nS
to nCP removal time.
D
,
D
1998 Apr 20
7
Page 8
Philips Semiconductors Product specification
Dual JK
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
flip-flop with set and reset; positive-edge trigger
74LV109
1998 Apr 20
8
Page 9
Philips Semiconductors Product specification
Dual JK
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
flip-flop with set and reset; positive-edge trigger
74LV109
1998 Apr 20
9
Page 10
Philips Semiconductors Product specification
Dual JK
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
flip-flop with set and reset; positive-edge trigger
74LV109
1998 Apr 20
10
Page 11
Philips Semiconductors Product specification
Dual JK
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
flip-flop with set and reset; positive-edge trigger
74LV109
1998 Apr 20
11
Page 12
Philips Semiconductors Product specification
Dual JK
flip-flop with set and reset; positive-edge trigger
DEFINITIONS
74LV109
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Copyright Philips Electronics North America Corporation 1998
print code Date of release: 05-96
Document order number: 9397-750-04417
All rights reserved. Printed in U.S.A.
1998 Apr 20
12
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