Page 1
INTEGRATED CIRCUITS
74LV107
Dual JK flip-flop with reset;
negative-edge trigger
Product specification
Supersedes data of 1997 Feb 03
IC24 Data Handbook
1998 Apr 20
Page 2
Philips Semiconductors Product specification
74L V107Dual JK flip-flop with reset; negative-edge trigger
FEA TURES
•Wide operating: 1.0 to 5.5 V
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
CC
CC
CC
= 3.3 V,
= 3.3 V,
•Output capability: standard
•I
category: flip-flops
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr = t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
nCP to nQ
nCP to nQ
nR to nQ, nQ
f
max
C
C
I
PD
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop VI = GND to V
NOTE:
1. C
is used to determine the dynamic power dissipation (PD in µW)
PD
= CPD × V
P
D
f
= input frequency in MHz; CL = output load capacitance in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
× V
L
2
× fi (CL × V
CC
2
× fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
2
fo) where:
CC
= 3.6 V
CL = 15 pF;
VCC = 3.3 V
DESCRIPTION
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and
function compatible with 74HC/HCT107.
The 74LV107 is a dual negative-edge triggered JK-type flip-flop
featuring individual J, K, clock (nCP
complementary Q and Q
outputs.
The J and K inputs must be stable one set-up time prior to the
HIGH-to-LOW clock transition for predictable operation.
The reset (nR
) is an asynchronous active LOW input. When LOW, it
overrides the clock and data inputs, forcing the Q output LOW and
the Q
output HIGH.
Schmitt-trigger action in the clock input makes the circuit highly
tolerant to slower clock rise and fall times.
1
CC
) and reset (nR) inputs; also
15
15
ns
15
30 pF
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
14-Pin Plastic DIL –40°C to +125°C 74LV107 N 74LV107 N SOT27-1
14-Pin Plastic SO –40°C to +125°C 74LV107 D 74LV107 D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +125°C 74LV107 DB 74LV107 DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +125°C 74LV107 PW 74LV107PW DH SOT402-1
PIN CONFIGURATION
1J
1
1Q
2
1Q
3
1K
4
2Q
5
2Q
6
GND
7
14
13
12
11
10
9
8
SV00497
V
CC
1R
1CP
2K
2R
2CP
2J
PIN DESCRIPTION
PIN
NUMBER
1, 8, 4, 11 1J, 2J, 1K, 2K Synchronous inputs; flip-flops 1 and 2
2, 6 1Q, 2Q Complement flip-flop outputs
3, 5 1Q, 2Q True flip-flop outputs
7 GND Ground (0 V)
12, 9 1CP, 2CP
13, 10 1R, 2R
14 V
SYMBOL FUNCTION
Clock input
(HIGH-to-LOW, edge-triggered)
Asynchronous reset inputs
(active LOW)
CC
Positive supply voltage
1998 Apr 20 853–1904 19255
2
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Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
LOGIC SYMBOL
11J
82J
12 1CP
9
41K
11 2K
J
CP
2CP
K
FUNCTIONAL DIAGRAM
1
1J
J
1291CP
4
13
CP
1K
K
1R
SV00498
1Q
1Q
31Q
52Q
21Q
62Q
3
2
Q
FF
Q
R
2R
1R
10
13
Q
FF1
Q
R
LOGIC SYMBOL (IEEE/IEC)
74LV107
1
12
4
13
8
9
11
10
1J
C1
1K
1R
2J
C1
2K
2R
3
2
5
6
SV00499
8
2CP
11
10
LOGIC DIAGRAM
2J
J
Q
FF2
CP
2K
K
2R
K
J
R
CP
Q
R
2Q
2Q
SV00500
5
6
C
C
C
C
C
C
C
C
Q
C
C
Q
SV00501
1998 Apr 20
3
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Philips Semiconductors Product specification
OPERATING MODES
Dual JK flip-flop with reset; negative-edge trigger
74LV107
FUNCTION TABLE
INPUTS OUTPUTS
nR nCP nJ nK nQ nQ
Asynchronous reset L X X X L H
Toggle H ↓ h h q q
Load “0” (reset) H ↓ l h L H
Load “1” (set) H ↓ h l H L
Hold “no change” H ↓ l l q q
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the HIGH-to-LOW CP transition.
X = don’t care
↓ = HIGH-to-LOW CP transition
ABSOLUTE MAXIMUM RATINGS
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
I
IK
I
OK
I
O
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
PARAMETER CONDITIONS RATING UNIT
1, 2
–0.5V < VO < VCC + 0.5V
25
mA
I
I
P
T
GND
stg
TOT
DC VCC or GND current for types with
,
– standard outputs 50
CC
Storage temperature range –65 to +150 °C
Power dissipation per package
– plastic DIL
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
for temperature range: –40 to +125°C
above +70°C derate linearly with 12 mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mA
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 5.5 V
CC
V
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times except for
f
Schmitt-trigger inputs
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
–40
–40
–
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
50
°C
ns/V
V
V
1998 Apr 20
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Philips Semiconductors Product specification
V
V
V
V
HIGH l
t
voltage all out uts
V
g
V
LOW l
t
voltage all out uts
V
g
V
CONDITION
P
nCP to nQ, nQ
Dual JK flip-flop with reset; negative-edge trigger
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. V oltages are referenced to GND (ground = 0 V).
SYMBOL P ARAMETER TEST CONDITIONS
VCC = 1.2 V 0.9 0.9
IH
HIGH level Input
voltage
VCC = 2.0 V 1.4 1.4
VCC = 2.7 to 3.6 V 2.0 2.0
VCC = 4.5 to 5.5 V 0.7V
VCC = 1.2 V 0.3 0.3
IL
LOW level Input
voltage
VCC = 2.0 V 0.6 0.6
VCC = 2.7 to 3.6 V 0.8 0.8
VCC = 4.5 to 5.5 0.3V
VCC = 1.2 V; VI = VIH or V
VCC = 2.0 V; VI = VIH or V
V
OH
evel outpu
;
VCC = 2.7 V; VI = VIH or V
p
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
OH
HIGH level output
voltage;
STANDARD
outputs
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
VCC = 1.2 V; VI = VIH or V
VCC = 2.0 V; VI = VIH or V
V
OL
evel outpu
;
VCC = 2.7 V; VI = VIH or V
p
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
LOW level output
voltage;
OL
STANDARD
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; flip-flops
I
VCC = 3.0 V; VI = VIH or V
VCC = 4.5 V; VI = VIH or V
VCC = 5.5 V; VI = VCC or GND 1.0 1.0 µA
VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80 µA
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
Additional
CC
quiescent supply
current per input
VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 100µA 4.3 4.5 4.3
–IO = 6mA 2.40 2.82 2.20
–IO = 12mA 3.60 4.20 3.50
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 6mA 0.25 0.40 0.50
IO = 12mA 0.35 0.55 0.65
-40°C to +85°C -40°C to +125°C
MIN TYP
CC
LIMITS
1
MAX MIN MAX
0.7V
CC
74LV107
CC
0.3V
UNIT
CC
V
V
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
SYMBOL PARAMETER WAVEFORM
t
PHL/tPLH
1998 Apr 20
LIMITS
–40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP
1
MAX MIN MAX
UNIT
1.2 95
2.0 32 44 56
ropagation delay
Figures 1, 2
2.7 24 33 41
3.0 to 3.6 18
2
26 33
ns
4.5 to 5.5 22 28
5
Page 6
Philips Semiconductors Product specification
SYMBOL
PARAMETER
WAVEFORM
UNIT
P
nR to nQ, nQ
t
Figure 2
ns
t
Figure 2
ns
R
nR to nCP
Set
nJ, nK to CP
Hold ti
nJ, nK to CP
f
Figure 1
MHz
Dual JK flip-flop with reset; negative-edge trigger
AC CHARACTERISTICS (Continued)
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ
CONDITION –40 to +85 °C –40 to +125 °C
VCC(V) MIN TYP
1.2 95
t
PHL/tPLH
W
W
t
rem
t
su
t
h
max
ropagation delay
Clock pulse width
HIGH or LOW
Reset pulse width
LOW
emoval time
-up time
me
Maximum clock
pulse frequency
Figures 1, 2
Figure 2
Figure 1
Figure 1
NOTES:
1. Unless otherwise stated, all typical values are measured at T
2. Typical values are measured at V
= 3.3 V.
CC
2.0 32 44 56
2.7 24 33 41
3.0 to 3.6 18
4.5 to 5.5 22 28
2.0 34 14 41
2.7 25 10 30
3.0 to 3.6 20 8
4.5 to 5.5 15 18
2.0 34 14 41
2.7 25 10 30
3.0 to 3.6 20 8
4.5 to 5.5 15
1.2 35
2.0 24 12 29
2.7 18 9 21
3.0 to 3.6 14 7
4.5 to 5.5 11 14
1.2 40
2.0 26 14 31
2.7 19 10 23
3.0 to 3.6 15 8
4.5 to 5.5 12 15
1.2 -10
2.0 5 –3 5
2.7 5 –2 5
3.0 to 3.6 5 –2
4.5 to 5.5 5 5
2.0 14 40 12
2.7 19 58 16
3.0 to 3.6 24 70
4.5 to 5.5 30 24
= 25°C
amb
1
MAX MIN MAX
2
26 33
2
2
2
2
2
2
74LV107
ns
24
24
ns
17
ns
18
ns
5
20
1998 Apr 20
6
Page 7
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V a n d ≤ 3.6 V;
= 0.5 × VCC at VCC < 2.7 V a n d ≥ 4.5 V;
V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
V
I
nJ, nK
INPUT
GND
nCP
INPUT
GND
V
OH
nQ
OUTPUT
V
OL
V
OH
nQ
OUTPUT
V
OL
The shaded areas indicate when the input is permitted to change for
predictable output performance.
Figure 1. Clock (nCP) to output (nQ, nQ) propagation delays,
the clock pulse width, the J and K to nCP
V
M
t
su
t
h
V
I
V
t
t
M
PHL
PLH
1/f
max
t
W
V
M
V
M
t
su
t
h
t
t
set-up and hold times
and the maximum clock pulse frequency.
PLH
PHL
SV00504
TEST CIRCUIT
t
V
cc
V
O
C
L
PULSE
GENERATOR
V
l
D.U.T.
R
T
Test Circuit for Outputs
DEFINITIONS
RL = Load resistor
CL = Load capacitance includes jig and probe capacitiance
RT = Termination resistance should be equal to Z
TEST
PLH/tPHL
V
CC
< 2.7V
2.7–3.6V
≥ 4.5 V V
V
V
2.7V
CC
CC
OUT
I
Figure 3. Load circuitry for switching times.
74LV107
50pF
RL= 1k
of pulse generators.
SV00902
V
I
nCP
INPUT
GND
INPUT
GND
V
OH
nQ
OUTPUT
V
OL
V
OH
nQ
OUTPUT
V
OL
t
t
V
M
PHL
W
V
M
V
I
nR
t
PLH
V
M
t
rem
SV00502
Figure 2. Reset (nR) input to output (nQ, nQ) propagation
delays, the reset pulse width and the nR
to nCP removal time.
1998 Apr 20
7
Page 8
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1
74LV107
1998 Apr 20
8
Page 9
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74LV107
1998 Apr 20
9
Page 10
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74LV107
1998 Apr 20
10
Page 11
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
74LV107
1998 Apr 20
11
Page 12
Philips Semiconductors Product specification
Dual JK flip-flop with reset; negative-edge trigger
DEFINITIONS
74LV107
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code Date of release: 05-96
Document order number: 9397-750-04416
1998 Apr 20
12
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