Datasheet 74LCX74TTR, 74LCX74MTR, 74LCX74M Datasheet (SGS Thomson Microelectronics)

74LCX74

LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP

WITH 5V TOLERANT INPUTS

■ 5V TOLERANT INPUTS

■ HIGH SPEED :

f

= 150 MHz (MAX.) at VCC = 3V

MAX

■ POWER DOWN PROTECTION ON INPUT S

AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 24mA (MIN) at VCC = 3V

OH

■ PCI BUS LEVELS GUARANT EED AT 2 4 mA

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATING VOLTAGE RANGE:

V

CC

PHL

(OPR) = 2.0V to 3.6V (1.5V Data

Retention)

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 74

■ LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);
MM > 200V

DESCRIPTION

The 74LCX74 is a low voltage CMOS DUAL
D-TYPE FLIP FLOP WITH PRESET AN D CL EAR
NON INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C

2

MOS
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for inputs.

TSSOPSOP

ORDER CODES

PACKAGE TUBE T & R

SOP 74LCX74M 74LCX74MTR

TSSOP 74LCX74TTR

A signal on the D INPUT is transferred to the Q
OUTPUT during the positive going transition of the
clock pulse.
CLR

and PR are independent of the clock and
accomplished by a l ow setting on the app ropriate
input.
It has same speed performance at 3. 3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against stat ic discharge, giving
them 2KV ESD immunity and transient excess
voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

1/11September 2001

74LCX74

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1, 13 1CLR
2, 12 1D, 2D Data Inputs
3, 11 1CK, 2CK Clock Input (LOW to HIGH, Edge Triggered)
4, 10 1PR

5, 9 1Q, 2Q True Flip-Flop Outputs
6, 8 1Q

7 GND Ground (0V)

14 V

, 2CLR Asynchronous Reset - Direct Input

, 2PR Asynchronous Set - Direct Input

, 2Q Complement Flip-Flop Outputs

CC

Positive Supply Voltage

TRUTH TABLE

INPUTS OUTPUTS

CLR

L H X X L H CLEAR

H L X X H L PRESET

LLXXHH
HHL LH
HHH HL

HHX

X : Don’t Care

2/11

PR DCKQ Q

Q

n

Q

n

FUNCTION

NO CHANGE

74LCX74

LOGIC DIAGRAM

This log i c diagram has not be used to esti m ate propaga tion delays

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V
V
V

I

I

OK

I

I

CC

I

GND

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

1) I

absolute ma xim um rating mu st be observed

O

2) V

< GND

O

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage (VCC = 0V)

O

DC Output Voltage (High or Low State) (note 1) -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current (note 2)
DC Output Current

O

DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature

stg

Lead Temperature (10 sec)

L

-0.5 to +7.0 V

-0.5 to +7.0 V

-0.5 to +7.0 V
V

- 50 mA

- 50 mA

± 50 mA
± 100 mA
± 100 mA

-65 to +150 °C
300 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V
V
V

I

OH

I

OH

T

dt/dv Input Rise and Fall Time (note 2) 0 to 10 ns/V

1) Truth T abl e guaranteed: 1.5V to 3.6V

2) V

from 0.8V to 2V at VCC = 3.0V

IN

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage (VCC = 0V)

O

Output Voltage (High or Low State) 0 to V

O

, I

High or Low Level Output Current (VCC = 3.0 to 3.6V)

OL

, I

High or Low Level Output Current (VCC = 2.7V)

OL

Operating Temperature

op

2.0 to 3.6 V
0 to 5.5 V
0 to 5.5 V

CC

± 24 mA
± 12 mA

-55 to 125 °C

V

3/11

74LCX74

DC SPECIFICATIONS

Test Condition Value

Symbol Parameter

IH

IL

OH

OL

I

I

off

CC

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

Low Level Output
Voltage

Input Leakage
Current

Power Off Leakage
Current

Quiescent Supply
Current

ICC incr. per Input

V

V

V

V

I

I

CC

∆I

V

CC

(V)

2.7 to 3.6

2.7 to 3.6

2.7

3.0

2.7 to 3.6

2.7

3.0

2.7 to 3.6

0

2.7 to 3.6

2.7 to 3.6

-40 to 85 °C -55 to 125 °C

Min. Max. Min. Max.

2.0 2.0 V

0.8 0.8 V

=-100 µAVCC-0.2 VCC-0.2

I

O

=-12 mA

I

O

I

=-18 mA

O

I

=-24 mA

O

=100 µA

I

O

I

=12 mA

O

I

=16 mA

O

I

=24 mA

O

= 0 to 5.5V

V

I

or VO = 5.5V

V

I

2.2 2.2

2.4 2.4

2.2 2.2

0.2 0.2

0.4 0.4

0.4 0.4

0.55 0.55
± 5 ± 5 µA

VI = VCC or GND

V

or VO= 3.6 to 5.5V

I

VIH = VCC - 0.6V

± 10 ± 10

500 500 µA

Unit

10 10 µA
10 10

µA

V

V

DYNAMIC SWITCHING CHARACTERISTICS

Test Condition Value

T

Symbol Parameter

V

OLP

V

OLV

1) Number of outputs d ef i ned as "n". Me asured with "n-1" output s switching from HIGH to LO W or LOW to HIGH. The remaini ng outpu t is
measur ed i n the LOW state.

Dynamic Low Level Quiet
Output (note 1)

V

3.3

CC

(V)

= 50pF

C

L

V

= 0V, VIH = 3.3V

IL

Min. Typ. Max.

= 25 °C

A

0.8

-0.8

Unit

V

4/11

AC ELECTRICAL CHARACTERISTICS

Test Condition Value

74LCX74

Symbol Parameter

t

PLH tPHL

t

PLH tPHL

t

t

t

Propagation Delay
Time (CK to Q or Q

Propagation Delay
Time (PR
Q or Q

Setup Time, HIGH or

S

LOW level D to CK
Hold Time, HIGH or

h

LOW level D to CK
CK Pulse Width,

W

HIGH or LOW

or CLR to

)

PR or CLR Pulse

C

R

t

V

CC

(V)

2.7

)

3.0 to 3.6 1.5 7.0 1.5 8.0

L

(pF)

(Ω)

50 500 2.5

= t

L

s

(ns)

2.7

3.0 to 3.6 1.5 7.0 1.5 8.0

2.7

3.0 to 3.6 2.5 3.5

2.7

3.0 to 3.6 1.5 1.5

50 500 2.5

50 500 2.5

50 500 2.5

2.7

3.0 to 3.6 3.0 4.0

50 500 2.5

-40 to 85 °C -55 to 125 °C

r

Min. Max. Min. Max.

1.5 8.0 1.5 9.2

1.5 8.0 1.5 9.2

2.5 3.5

1.5 1.5

3.0 4.0

Unit

ns

ns

ns

ns

ns

Width, LOW

t

rec

f

MAX

t

OSLH

t

OSHL

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch­ing in the same direction, either HIGH or LOW (t

2) Param eter guaran te ed by design

Recovery Time PR
or CLR

to CK

Clock Pulse
Frequency

Output To Output
Skew Time (note1,

2)

2.7

3.0 to 3.6 0 0

50 500 2.5

00

ns

2.7 50 500 2.5 150 150 MHz

3.0 to 3.6 50 500 2.5 1.0 1.0 ns

OSLH

= | t

PLHm

- t

PLHn

|, t

OSHL

= | t

PHLm

- t

PHLn

|)

CAPACITIVE CHARACTERISTICS

Test Condition Value

T

Symbol Parameter

C

C

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without

load. (R ef er to Test Circui t). Averag e operating cu rrent can be obtained by the foll owing equat io n. I
Flip-Flop)

Input Capacitance

IN

Power Dissipation Capacitance

PD

(note 1)

V

CC

(V)

3.3

VIN = 0 to V

3.3 fIN = 10MHz
V

= 0 or V

IN

Min. Typ. Max.

CC

CC

CC(opr)

= 25 °C

A

Unit

6pF

40

= CPD x VCC x fIN + ICC/2 (per

pF

5/11

74LCX74

TEST CIRCUIT

CL = 50 pF or equival ent (includes jig and probe capacitance)
R

= 500Ω or equivalent

L

R

= Z

of pulse generator (typically 50Ω)

T

OUT

WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)

6/11

WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle )

74LCX74

7/11

74LCX74

WAVEFORM 3 : RECOVERY TIMES (f=1MHz; 50% duty cycle)

WAVEFORM 4 : PU LSE WIDTH (f=1MHz; 50% duty cycle)

8/11

SO-14 MECHANICAL DATA

74LCX74

DIM.

A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064

b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010

C 0.5 0.019
c1 45° (typ.)

D 8.55 8.75 0.336 0.344

E 5.8 6.2 0.228 0.244

e 1.27 0.050
e3 7.62 0.300

F 3.8 4.0 0.149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.68 0.026

S8° (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

PO13G

9/11

74LCX74

TSSOP14 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0089

D 4.9 5 5.1 0.193 0.197 0.201

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0° 8°0° 8°

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

c

K

L

E

D

E1

PIN 1 IDENTIFICATION

10/11

1

0080337D

74LCX74

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11/11