Datasheet 74LCX652MSA, 74LCX652CW, 74LCX652WMX, 74LCX652WM, 74LCX652MTCX Datasheet (Fairchild Semiconductor)

...

Download

Page 1

February 1994 Revised April 1999

74LCX652 Low Voltage Transceiver/Register with 5V Tolerant Inputs and Outputs

74LCX652 Low Voltage Transceiver/Register with 5V Tolerant

Inputs and Outputs

General Description

The LCX652 consists of bus transceiver circuits with Dtype flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from internal registers. Data on the A or B bus will be clocked into the registers a s the appropr iate clock pin g oes to the HIGH logic level. Output Enable pins (OEAB, OEBA

) are

provided to control the transceiver function. The LCX652 is designed for low voltage (2.5V or 3.3V) V

applications with capability of interfacing to a 5V signal environment.

The LCX652 is fabrica ted with an advanced CMOS technology to achieve high spee d operation while mai ntaining CMOS low power dissipation.

Features

■ 5V tolerant inputs and outputs

■ 2.3V − 3.6V V

specifications provided

■ 7.0 ns t

max (VCC = 3.3V), 10 µA ICC max

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ ±24 mA output drive (V

= 3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model > 2000V Machine model > 200V

Note 1: To ensure the high-impedan c e state during power up or down, OE should be tied to VCC through a pull-up res istor: the m inimu m value or t he

resistor is determin ed by the current-sourcing capability of the dr iv er.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

74LCX652WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74LCX652MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LCX652MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

0–A7

, B0–B7A and B Inputs/3-STATE Outputs CPAB, CPBA Clock Inputs SAB, SBA Select Inputs OEAB, OEBA

Output Enable Inputs

Page 2

www.fairchildsemi.com 2

74LCX652

Logic Symbols

IEEE/IEC

Truth Table

(Note 2)

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial



= LOW-to-HIGH Clock Transition

Note 2: The data output fu nction s may b e enable d or di sabled b y variou s signa ls at OEA B or O EBA

inputs. Data input function s are a lways e nabled, i.e.,

data at the bus pins w ill be stored on every LOW- to -H I GH t ransition on the clock inputs.

Inputs Inputs/Outputs Operating Mode

OEAB OEBA

CPAB CPBA SAB SBA A0 thru A

B0 thru B

L H H or L H or L X X Input Input Isolation LH



X X Store A and B Data



H or L X X Input Not Specified Store A, Hold B



X X Input Output Store A in Both Registers

LXH or L



X X Not Specified Input Hold A, Store B



X X Output Input Store B in Both Registers L L X X X L Output Input Real-Time B Data to A Bus L L X H or L X H Store B Data to A Bus H H X X L X Input Output Real-Time A Data to B Bus H H H or L X H X Stored A Data to B Bus H L H or L H or L H H Output Output Stored A Data to B Bus and

Stored B Data to A Bus

Page 3

3 www.fairchildsemi.com

74LCX652

Functional Description

In the transceiver mode , data present a t the HIGH impe dance port may be sto red in either the A or B register or both.

The select (SAB, SBA) controls can multiplex stored and real-time.

The examples below demonstrate the four fundamental bus-management fun cti on s t hat c an be performed w ith t he Octal bus transceiver and receiver.

Data on the A or B data bus, or both can be stored in the internal D flip-flop by LOW to HIGH transitions at the appropriate Clock Inp uts (CPAB, CPBA) regardless of the Select or Output Enable Inputs. When SAB and SBA are in the real time transfer m od e, it is a lso po ssibl e to sto re d ata without using the internal D flip-flops by simultaneously enabling OEAB and OEBA

. In this configuration each Output reinforces its Input. Thus when all other data sources to the two sets of bus lines a re in a HIGH impedance state , each set of bus lines will remain at its last state.

Real-Time Transfer

Bus B to Bus A

Transfer Storage

Data to A or B

Real-Time Transfer

Bus A to Bus B

Storage

OEAB OEBA

CPAB CPBA SAB SBA

LLXXXL

OEAB OEBA

CPAB CPBA SAB SBA

H L H or L H or L H H

OEAB OEBA CPAB CPBA SAB SBA

HHXXLX

OEAB OEBA

CPAB CPBA SAB SBA



XXX

LXX





Page 4

www.fairchildsemi.com 4

74LCX652

Logic Diagram

Please note that this diagram is provided o nly f or t he understanding of lo gic operations and should not be used to estimate propagation delays.

Page 5

5 www.fairchildsemi.com

74LCX652

Absolute Maximum Ratings(Note 3)

Recommended Operating Conditions (Note 5)

Note 3: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating C onditions” table will def ine the conditions for act ual device operation.

Note 4: I

Absolute Maximum Rating must be observed.

Note 5: Unused inputs or I/Os must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

Supply Voltage −0.5 to +7.0 V

DC Input Voltage −0.5 to +7.0 V

DC Output Voltage −0.5 to +7.0 Output in 3-STATE

−0.5 to V

+ 0.5 Output in HIGH or LOW State (Note 4)

DC Input Diode Current −50 VI < GND mA

DC Output Diode Current −50 VO < GND

+50 V

> V

DC Output Source/Sink Current ±50 mA

DC Supply Current per Supply Pin ±100 mA

GND

DC Ground Current per Ground Pin ±100 mA

STG

Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

Supply Voltage Operating 2.0 3.6

Data Retention 1.5 3.6

Input Voltage 0 5.5 V

Output Voltage HIGH or LOW State 0 V

3-STATE 0 5.5

OH/IOL

Output Current VCC = 3.0V − 3.6V ±24

mAV

= 2.7V − 3.0V ±12

= 2.3V − 2.7V ±8

Free-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate, V

= 0.8V − 2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions

TA = −40°C to +85°C

Units

(V) Min Max

HIGH Level Input Voltage 2.3 − 2.7 1.7

2.7 − 3.6 2.0

LOW Level Input Voltage 2.3 − 2.7 0.7

2.7 − 3.6 0.8

HIGH Level Output Voltage IOH = −100 µA2.3 − 3.6 VCC − 0.2

IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2

LOW Level Output Voltage IOL = 100 µA2.3 − 3.6 0.2

IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 IOL = 24 mA 3.0 0.55

Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA

3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0

µA

VI = VIH or V

OFF

Power-Off Leakage Current VI or VO = 5.5V 0 10 µA

Page 6

www.fairchildsemi.com 6

74LCX652

DC Electrical Characteristics (Continued)

Note 6: Outputs dis abled or 3-STATE only.

AC Electrical Characteristics

Note 7: Skew is defined as t he absolute value of t he difference betwee n t he actual propag at ion delay for any tw o separate outpu ts of the same device. T he

specification applies to any outputs switching in the same direction, eit her HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

). Parameter guaranteed by design.

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions

TA = −40°C to +85°C

Units

(V) Min Max

Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 10

µA

3.6V ≤ VI, VO ≤ 5.5V (Note 6) 2.3 − 3.6 ±10

∆I

Increase in ICC per Input VIH = VCC −0.6V 2.3 − 3.6 500 µA

Symbol Parameter

TA = −40°C to +85°C; RL = 500Ω

Units

VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V

CL = 50 pF CL = 50 pF CL = 30 pF

Min Max Min Max Min Max

MAX

Maximum Clock Frequency 150 MHz

PHL

Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4

PLH

Bus to Bus 1.5 7.0 1.5 8.0 1.5 8.4

PHL

Propagation Delay 1.5 8.5 1.5 9.5 1.5 10.5

PLH

Clock to Bus 1.5 8.5 1.5 9.5 1.5 10.5

PHL

Propagation Delay 1.5 8.5 1.5 9.5 1.5 10.5

PLH

Select to Bus 1.5 8.5 1.5 9.5 1.5 10.5

PZL

Output Enable Time 1.5 8.5 1.5 9.5 1.5 10.5

PZH

1.5 8.5 1.5 9.5 1.5 10.5

PLZ

Output Disable Time 1.5 8.5 1.5 9.5 1.5 10.5

PHZ

1.5 8.5 1.5 9.5 1.5 10.5

Setup Time 2.5 2.5 4.0 ns

Hold Time 1.5 1.5 2.0 ns

Pulse Width 3.3 3.3 4.0 ns

OSHL

Output to Output Skew (Note 7) 1.0

OSLH

1.0

Symbol Parameter Conditions

(V)

TA = 25°C

Units

Typical

OLP

Quiet Output Dynamic Peak V

CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6

OLV

Quiet Output Dynamic Valley V

CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6

Symbol Parameter Conditions Typical Units

Input Capacitance VCC = Open, VI = 0V or V

7pF

I/O

Input/Output Capacitance VCC = 3.3V, VI = 0V or V

8pF

Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF

Page 7

7 www.fairchildsemi.com

74LCX652

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (C

includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and t

rec

Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

rise

and t

fall

FIGURE 2. Waveforms

(Input Characteristics; f =1MHz, t

= tF = 3ns)

Test Switch

PLH

, t

PHL

Open

PZL

, t

PLZ

6V at VCC = 3.3 ± 0.3V V

x 2 at VCC = 2.5 ± 0.2V

PZH,tPHZ

GND

Symbol

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

1.5V 1.5V VCC/2

VOL + 0.3V VOL + 0.3V VOL + 0.15V

VOH − 0.3V VOH − 0.3V VOH − 0.15V

Page 8

www.fairchildsemi.com 8

74LCX652

Schematic Diagram Generic for LCX Family

Page 9

9 www.fairchildsemi.com

74LCX652

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

Package Number M24B

24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA24

Page 10

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74LCX652 Low Voltage Transceive r/Register with 5V T olerant Inputs and Outputs

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are device s or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component in any compon ent of a l ife supp ort device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24