Datasheet 74LCX543CW, 74LCX543WMX, 74LCX543WM, 74LCX543MTCX, 74LCX543MTC Datasheet (Fairchild Semiconductor)

...

Download

Page 1

May 1995 Revised April 1999

74LCX543 Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs

74LCX543 Low Voltage Octal Registered Transceiver with

5V Tolerant Inputs and Outputs

General Description

The LCX543 is a n on- inve rtin g octal transceiver contai n ing two sets of D-type register s for temporary storage o f data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow.

The LCX543 is designed for low voltage (2.5V or 3.3V) V

applications with capability of interfacing to a 5V signal environment.

The LCX543 is fabrica ted with an advanced CMOS technology to achieve high spee d operation while mai ntaining CMOS low power dissipation.

Features

■ 5V tolerant inputs and outputs

■ 2.3V − 3.6V V

specifications provided

■ 7.0 ns t

max (VCC = 3.3V), 10 µA ICC max

■ Power down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ ±24 mA Output Drive (V

= 3.0V)

■ Implements patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 500 mA

■ ESD performance:

Human body model > 2000V Machine model > 200V

Note 1: To ensure the high-impedan c e state during power up or do w n, OE should be tied to VCC through a pull-up res istor: the m inimu m value or t he

resistor is determin ed by the current-sourcin g c apability of the driver.

Ordering Code:

Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.

Connection Diagram Pin Descriptions

Order Number Package Number Package Description

74LCX543WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide 74LCX543MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LCX543MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Pin Names Description

OEAB

A-to-B Output Enable Input (Active LOW)

OEBA

B-to-A Output Enable Input (Active LOW)

CEAB

A-to-B Enable Input (Active LOW)

CEBA

B-to-A Enable Input (Active LOW)

LEAB

A-to-B Latch Enable Input (Active LOW)

LEBA

B-to-A Latch Enable Input (Active LOW)

0–A7

A-to-B Data Inputs or B-to-A 3-STATE Outputs

0–B7

B-to-A Data Inputs or A-to-B 3-STATE Outputs

Page 2

www.fairchildsemi.com 2

74LCX543

Logic Symbols

IEEE/IEC

Data I/O Control Table

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown ; B-to-A flow control is the same, except using CEBA

, LEBA and OEBA

Functional Description

The LCX543 contains two sets of eight D-type latches, with separate input and output co ntrols for each set. For data flow from A to B, for example, th e A-to-B Enable (CEAB

)

input must be LOW in order to ent er data from A

0–A7

take data from B

0–B7

, as indicated in the Data I/ O Control

Ta b l e. With CEAB

LOW, a LOW signal on the A-to-B La tch

Enable (LEAB

) input makes the A-to-B latches transparent;

a subsequent LOW-to-HIGH transi tion of the LEAB

signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB

and OEAB both LOW, the 3-STATE B output buffers are acti ve and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA

LEBA

and OEBA inputs.

Logic Diagram

Please note that this diagram is provided only f or t he understanding of logic operations and should not be used to estimate propagation delays.

Inputs Latch Status Output Buffers

CEAB

LEAB OEAB

H X X Latched High Z X H X Latched — L L X Transparent — X X H — High Z L X L — Driving

Page 3

3 www.fairchildsemi.com

74LCX543

Absolute Maximum Ratings(Note 2)

Recommended Operating Conditions (Note 4)

Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated

at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating C onditions” table will define the conditions for actua l dev ic e operation.

Note 3: I

Absolute Maximum Rating must be observed.

Note 4: Unused inputs or I/O's must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Symbol Parameter Value Conditions Units

Supply Voltage −0.5 to +7.0 V

DC Input Voltage −0.5 to +7.0 V

DC Output Voltage −0.5 to +7.0 Output in 3-STATE

−0.5 to V

+ 0.5 Output in HIGH or LOW State (Note 3)

DC Input Diode Current −50 VI < GND mA

DC Output Diode Current −50 VO < GND

+50 V

> V

DC Output Source/Sink Current ±50 mA

DC Supply Current per Supply Pin ±100 mA

GND

DC Ground Current per Ground Pin ±100 mA

STG

Storage Temperature −65 to +150 °C

Symbol Parameter Min Max Units

Supply Voltage Operating 2.0 3.6

Data Retention 1.5 3.6

Input Voltage 05.5V

Output Voltage HIGH or LOW State 0 V

3-STATE 0 5.5

OH/IOL

Output Current VCC = 3.0V − 3.6V ±24

mAV

= 2.7V − 3.0V ±12

= 2.3V − 2.7V ±8

Free-Air Operating Temperature −40 85 °C

∆t/∆V Input Edge Rate, V

= 0.8V − 2.0V, VCC = 3.0V 0 10 ns/V

Symbol Parameter Conditions

TA = −40°C to +85°C

Units

(V) Min Max

HIGH Level Input Voltage 2.3 − 2.7 1.7

2.7 − 3.6 2.0

LOW Level Input Voltage 2.3 − 2.7 0.7

2.7 − 3.6 0.8

HIGH Level Output Voltage IOH = −100 µA2.3 − 3.6 VCC − 0.2

IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2

LOW Level Output Voltage IOL = 100 µA2.3 − 3.6 0.2

IOL = 8mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 IOL = 24 mA 3.0 0.55

Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA

3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0

µA

VI = VIH or V

OFF

Power-Off Leakage Current VI or VO = 5.5V 0 10 µA

Page 4

www.fairchildsemi.com 4

74LCX543

DC Electrical Characteristics (Continued)

Note 5: Outputs dis abled or 3-STATE only.

AC Electrical Characteristics

Note 6: Skew is defined as t he absolute value of t he difference between the actual propagation delay for any two separate outputs o f the same device. The

specification applies to any outputs switc hing in the same direction, eit her HIGH-to-LOW (t

OSHL

) or LOW-to-HIGH (t

OSLH

Dynamic Switching Characteristics

Capacitance

Symbol Parameter Conditions

TA = −40°C to +85°C

Units

(V) Min Max

Quiescent Supply Current VI = VCC or GND 2.3 − 3.6 10

µA

3.6V ≤ VI, VO ≤ 5.5V (Note 5) 2.3 − 3.6 ±10

∆I

Increase in ICC per Input VIH = VCC −0.6V 2.3 − 3.6 500 µA

Symbol Parameter

TA = −40°C to +85°C, RL = 500Ω

Units

VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V

CL = 50 pF CL = 50 pF CL = 30 pF

Min Max Min Max Min Max

PHL

Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4

PLH

An to Bn or Bn to A

1.5 7.0 1.5 8.0 1.5 8.4

PHL

Propagation Delay 1.5 8.5 1.5 9.5 1.5 10.5

PLH

LEBA to An or LEAB to B

1.5 8.5 1.5 9.5 1.5 10.5

PZL

Output Enable Time 1.5 9.0 1.5 10.0 1.5 11.0

PZH

OEBA or OEAB to An or B

1.5 9.0 1.5 10.0 1.5 11.0

CEBA or CEAB to An or B

PLZ

Output Disable Time 1.5 7.0 1.5 7.5 1.5 8.4

PHZ

OEBA or OEAB to An or B

1.5 7.0 1.5 7.5 1.5 8.4

CEBA or CEAB to An or B

Setup Time, HIGH or LOW Data to LEXX

2.5 2.5 4.0 ns

Hold Time, HIGH or LOW Data to LEXX

1.5 1.5 2.0 ns

Pulse Width, Latch Enable, LOW 3.3 3.3 3.3 ns

OSHL

Output to Output Skew 1.0

OSLH

(Note 6) 1.0

Symbol Parameter Conditions

(V)

TA = 25°C

Units

Typical

OLP

Quiet Output Dynamic Peak V

CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6

OLV

Quiet Output Dynamic Valley V

CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8

CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6

Symbol Parameter Conditions Typical Units

Input Capacitance VCC = Open, VI = 0V or V

7pF

I/O

Input/Output Capacitance VCC = 3.3V, VI = 0V or V

8pF

Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 25 pF

Page 5

5 www.fairchildsemi.com

74LCX543

AC LOADING and WAVEFORMS Generic for LCX Family

FIGURE 1. AC Test Circuit (C

includes probe and jig capacitance)

Waveform for Inverting and Non-Inverting Functions

Propagation Delay. Pulse Width and t

rec

Waveforms

3-STATE Output Low Enable and

Disable Times for Logic

3-STATE Output High Enable and

Disable Times for Logic

Setup Time, Hold Time and Recovery Time for Logic

rise

and t

fall

FIGURE 2. Waveforms

(Input Characteristics; f =1MHz, t

= tF = 3ns)

Test Switch

PLH

, t

PHL

Open

PZL

, t

PLZ

6V at VCC = 3.3 ± 0.3V V

x 2 at VCC = 2.5 ± 0.2V

PZH,tPHZ

GND

Symbol

3.3V ± 0.3V 2.7V 2.5V ± 0.2V

1.5V 1.5V VCC/2

VOL + 0.3V VOL + 0.3V VOL + 0.15V

VOH − 0.3V VOH − 0.3V VOH − 0.15V

Page 6

www.fairchildsemi.com 6

74LCX543

Schematic Diagram Generic for LCX Family

Page 7

7 www.fairchildsemi.com

74LCX543

Physical Dimensions inches (millimeters) unless otherwise noted

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

Package Number M24B

24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA24

Page 8

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74LCX543 Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the user.

2. A critical component i n any compon ent of a lif e support device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort device or system, or to affect its safety or effectiveness.

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC24