LOW VOLTAGE CMOS 1 6 -BIT D-TYPE FLIP-FLOP (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
■ 5V TOLERANT INPUTS AND OUTPUTS
■ HIGH SPEED :
f
= 150MHz (MIN.) at VCC=3V
MAX
■ POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
|=IOL= 24mA (MIN) at VCC=3V
OH
■ PCI BUS LEVELS GUARANTEED AT 24 mA
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
PHL
■ OPERATING VOLTAGE RANGE:
V
(OPR) = 2.0V to 3.6V (1.5V Data
CC
Retention)
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16374
■ LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
■ ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
ORDER CODES
PACKAGETUBET & R
TSSOP74LCX16374TTR
PIN CO NNE CTION
TSSOP
DESCRIPTION
The 74LCX16374 is a low voltage CM OS 16 BIT
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
silicon gat e and double-layer metal wiring C
2
MOS
technology. I t is ideal for low power and high
speed 3. 3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE flip-flops are co ntrolled by
two clock inputs (nCK) and two output enable inputs(nOE
). On the positive transition of the (nCK),
the nQ outputs will be set to the logic state that
were setup at the nD inputs. While the (nOE
) input
is low, the 8 outputs (nQ) wil l be i n a normal state
(high or low logic level) and while high level the
outputs will be in a high impedance state.
Any output con trol does not affect the internal operation of flip flops; that is, the old data can be retained or the new data can be entered even while
the outputs are off.
It has same speed performance at 3.3V than 5V
AC/ACT family, c ombined with a lower power
consumption.
All inputs and outputs are equippe d with protection circuits against static discharge, giving them
2KV ESD immunity and transient excess vo ltage.
1/10February 2003
Page 2
74LCX16374
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN NoSYMBOLNAME AND FUNCTION
11OE
2, 3,5,6,8,9,
11, 12
13,14, 16,17,
19, 20, 22, 23
242OE
252CKLatch Enable Input
36,35, 33,32,
30, 29, 27, 26
47,46, 44,43,
41, 40, 38, 37
481CKLatch Enable Input
4, 10, 15, 21,
28, 34, 39, 45
7, 18, 31, 42V
1Q0 to 1Q7 3-State Outputs
2Q0 to 2Q7 3-State Outputs
2D0 to 2D7 Data Inputs
1D0 to 1D7 Data Inputs
GNDGround (0V)
CC
3 State Output Enable
Input (Active LOW)
3 State Output Enable
Input (Active LOW)
Positive Supply Voltage
TRUTH TABLE
INPUTSOUTPUT
OE
HXXZ
LXNO CHANGE*
LLL
LHH
X : Don‘t Care
Z : High Impedance
CKDQ
IEC LOGIC SYMBOLS
2/10
Page 3
74LCX16374
LOGIC DIAGRAM
This logic diagram has not to be used to estimate propagation delays
ABSOLUTE MAXIMUM RATINGS
SymbolParameterValueUnit
V
V
V
V
I
I
OK
I
I
CC
I
GND
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
absolute maximum rating must be observed
1) I
O
<GND
2) V
O
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage (OFF State)
O
DC Output Voltage (High or Low State) (note 1)-0.5 to VCC+ 0.5
O
DC Input Diode Current
IK
DC Output Diode Current (note 2)
DC Output Current
O
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
stg
Lead Temperature (10 sec)
L
-0.5 to +7.0V
-0.5 to +7.0V
-0.5 to +7.0V
V
-50mA
-50mA
± 50mA
± 100mA
± 100mA
-65 to +150°C
300°C
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
V
I
OH,IOL
I
OH,IOL
T
dt/dvInput Rise and Fall Time (note 2)0 to 10ns/V
1) Truth Table guaranteed: 1.5V to 3.6V
from0.8Vto 2V at VCC=3.0V
2) V
IN
Supply Voltage (note 1)
CC
Input Voltage
I
Output Voltage (OFF State)
O
Output Voltage (High or Low State)0 to V
O
High or Low Level Output Current (VCC= 3.0 to 3.6V)
High or Low Level Output Current (VCC= 2.7V)
Operating Temperature
op
2.0 to 3.6V
0 to 5.5V
0 to 5.5V
CC
± 24mA
± 12mA
-55 to 125°C
V
3/10
Page 4
74LCX16374
DC SPECIFICATIONS
Test ConditionValue
SymbolParameter
V
V
V
V
I
I
OZ
High Level Input
IH
Voltage
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
Input Leakage
I
I
Current
Power Off Leakage
off
Current
High Impedance
Output Leakage
Current
I
CC
∆I
Quiescent Supply
Current
ICCincr. per Input
CC
V
CC
(V)
2.7to3.6
2.7to3.6
2.7
3.0
2.7to3.6
2.7
3.0
2.7to3.6
0
2.7to3.6
2.7to3.6
2.7to3.6
-40to85°C-55to125°C
Min.Max.Min.Max.
2.02.0V
0.80.8V
IO=-100 µAVCC-0.2VCC-0.2
=-12 mA
I
O
I
=-18 mA
O
=-24 mA
I
O
IO=100 µA
I
=12 mA
O
I
=16 mA
O
=24 mA
I
O
V
= 0 to 5.5V
I
or VO=5.5V
V
I
I=VIH
or V
V
VO= 0 to V
VI=VCCor GND
or VO= 3.6 to 5.5V
V
I
VIH=VCC-0.6V
IL
CC
2.22.2
2.42.4
2.22.2
0.20.2
0.40.4
0.40.4
0.550.55
± 5± 5µA
1010µA
± 5± 5µA
2020
± 20± 20
500500µA
Unit
V
V
µA
DYNAMIC SWITCHING CHARA CTERISTICS
Test ConditionValue
=25°C
SymbolParameter
V
CC
(V)
V
OLP
V
OLV
1) Number of outputsdefined as "n".Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH.The remainingoutputis
measured in the LOW state.
Dynamic Low Level Quiet
Output (note 1)
3.3
=50pF
C
L
V
=0V,VIH= 3.3V
IL
4/10
T
A
Min.Typ.Max.
0.8
-0.8
Unit
V
Page 5
AC ELECTRICAL C HARACTERISTICS
74LCX16374
Test ConditionValue
SymbolParameter
V
CC
(V)
t
PLHtPHL
t
PZLtPZH
Propagation Delay
Time
Output Enable Time
to HIGH and LOW
level
t
PLZtPHZ
Output Disable Time
from HIGHand LOW
level
t
Set-Up Time, HIGH
S
or LOW level
(DntoCK)
t
Hold Time, HIGH or
h
LOW level
(DntoCK)
t
f
MAX
t
OSLH
t
OSHL
1) Skew is defined as the absolutevalue of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (t
2) Parameter guaranteed by design
CK Pulse Width,
W
HIGH or LOW
Clock Pulse
Frequency
Output To Output
Skew Time (note1,
2)
2.7
3.0 to 3.61.56.21.56.2
2.7
3.0 to 3.61.56.11.56.1
2.7
3.0 to 3.61.56.01.56.0
2.7
3.0 to 3.62.52.5
2.7
3.0 to 3.61.51.5
2.7
3.0 to 3.63.03.0
3.0 to 3.6505002.5170150MHz
3.0 to 3.6505002.51.01.0ns
OSLH
C
L
(pF)
505002.5
505002.5
505002.5
505002.5
505002.5
505002.5
=|t
PLHm-tPLHn
R
(Ω)
|, t
L
OSHL
t
s
(ns)
= t
=|t
-40 to 85 °C-55 to 125 °C
r
Min.Max.Min.Max.
1.56.51.56.5
1.56.31.56.3
1.56.21.56.2
2.52.5
1.51.5
3.03.0
PHLm-tPHLn
|)
Unit
ns
ns
ns
ns
ns
ns
CAPACITIVE CHARACTERISTICS
Test ConditionValue
=25°C
SymbolParameter
V
CC
(V)
C
C
OUT
C
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
circuit)
Input Capacitance
IN
Output Capacitance
Power Dissipation Capacitance
PD
(note 1)
3.3
3.3
VIN= 0 to V
VIN= 0 to V
3.3fIN= 10MHz
V
= 0 or V
IN
CC
CC
CC
T
A
Min.Typ.Max.
7pF
8pF
20
CC(opr)=CPDxVCCxfIN+ICC
Unit
pF
/16 (per
5/10
Page 6
74LCX16374
TEST CIRCUIT
TESTSWITCH
t
PLH,tPHL
t
PZL,tPLZ
t
PZH,tPHZ
CL= 50 pF or equivalent (includes jig and probe capacitance)
=R1=500Ω or equivalent
R
L
R
T=ZOUT
of pulse generator (typically 50Ω)
Open
6V
GND
WAVEFORM 1 : PROPAGATION DEL AYS, SETUP AND HOLD TIMES, MAXIMUM CLOCK
FREQUENCY (f=1MHz; 50% duty cycle)
6/10
Page 7
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
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