Datasheet 74LCX16373TTR Datasheet (SGS Thomson Microelectronics)

74LCX16373

LOW VOLTAGE CMOS 16-BIT D-TYPE LATCH (3-STATE)

WITH 5V TOLERANT INPUTS AND OUTPUTS

■ 5V TOLERANT INPUTS AND OUTPUTS

■ HIGH SPEED :

t

= 5.4 ns (MAX.) at VCC=3V

PD

■ POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

|=IOL= 24mA (MIN) at VCC=3V

OH

■ PCI BUS LEVELS GUARANTEED AT 24 mA

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOLTAGE RAN GE:

V

(OPR) = 2.0V to 3.6V (1.5V D ata

CC

Retention)

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 16373

■ LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

■ ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);
MM > 200V

ORDER CODES

PACKAGE TUBE T & R

TSSOP 74LCX16373TTR

PIN CO NNE CTION

TSSOP

DESCRIPTION

The 74LCX16373 is a low voltage CMOS 16 BIT
D-TYPE LATCH with 3 STATE OUTPUTS NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C

2

MOS
technology. It is ideal for low power and hi gh
speed 3. 3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 16 bit D-TYPE latches are byte controlled
by two latch enable inputs (nLE) and two output
enable inputs(OE

).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken LOW, the nQ outputs will
be latched precisely at the logic level of D input
data.
While the (nOE

) input is low, the nQ outputs wi ll be
in a normal logic state (high or low logic level) and
while high levelthe outputs w ill be in a high imped­ance state.
It has same speed performance at 3.3V than 5V
AC/ACT family, com bined with a lower power
consumption.
All inputs and outputs are equipped with prot ec ­tion circuits against static disc harge, giving them
2KV ESD immunity and transient excess vo ltage.

1/10February 2003

74LCX16373

INPUT AND OUTPUT EQUIVALENT CIRCUIT

PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

1 1OE

2, 3,5,6,8,9,

11, 12

13,14,16, 17,

19, 20, 22, 23

24 2OE

25 2LE Latch Enable Input

36,35,33, 32,

30, 29, 27, 26

47,46,44, 43,

41, 40, 38, 37

48 1LE Latch Enable Input

4, 10, 15, 21,
28, 34, 39, 45

7, 18, 31, 42 V

1Q0 to 1Q7 3-State Outputs

2Q0 to 2Q7 3-State Outputs

2D0 to 2D7 Data Inputs

1D0 to 1D7 Data Inputs

GND Ground (0V)

CC

3 State Output Enable
Input (Active LOW)

3 State Output Enable
Input (Active LOW)

Positive Supply Voltage

TRUTH TABLE

INPUTS OUTPUT

OE

HXX Z

L L X NO CHANGE *
LHL L
LHH H

X : Don‘t Care
Z : High Impedance
* : Q outputs arelatched atthetime whentheLE inputis taken low
logiclevel.

LE D Q

IEC LOGIC SYMBOLS

2/10

74LCX16373

LOGIC DIAGRAM

This logic diagram has not to be used to estimate propagation delays

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

V

V
V
V

I

I

OK

I

I

CC

I

GND

T

T

Absolute Maximum Ratings are those values beyond which damage tothe device may occur. Functional operation under these conditions is
not implied

absolute maximum rating must be observed

1) I

O

<GND

2) V

O

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage (OFF State)

O

DC Output Voltage (High or Low State) (note 1) -0.5 to VCC+ 0.5

O

DC Input Diode Current

IK

DC Output Diode Current (note 2)
DC Output Current

O

DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature

stg

Lead Temperature (10 sec)

L

-0.5 to +7.0 V

-0.5 to +7.0 V

-0.5 to +7.0 V
V

-50 mA

-50 mA

± 50 mA
± 100 mA
± 100 mA

-65 to +150 °C
300 °C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

V

V
V
V

I

OH,IOL

I

OH,IOL

T

dt/dv Input Rise and Fall Time (note 2) 0 to 10 ns/V

1) Truth Table guaranteed: 1.5V to 3.6V
from0.8V to 2Vat VCC=3.0V

2) V

IN

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage (OFF State)

O

Output Voltage (High or Low State) 0 to V

O

High or Low Level Output Current (VCC= 3.0 to 3.6V)
High or Low Level Output Current (VCC= 2.7V)
Operating Temperature

op

2.0 to 3.6 V
0 to 5.5 V
0 to 5.5 V

CC

± 24 mA
± 12 mA

-55 to 125 °C

V

3/10

74LCX16373

DC SPECIFICATIONS

Test Condition Value

Symbol Parameter

V

V

V

V

I

I

OZ

High Level Input

IH

Voltage
Low Level Input

IL

Voltage
High Level Output

OH

Voltage

Low Level Output

OL

Voltage

Input Leakage

I

I

Current
Power Off Leakage

off

Current
High Impedance

Output Leakage
Current

I

CC

∆I

Quiescent Supply
Current

ICCincr. per Input

CC

V

CC

(V)

2.7to3.6

2.7to3.6

2.7

3.0

2.7to3.6

2.7

3.0

2.7to3.6

0

2.7to3.6

2.7to3.6

2.7to3.6

-40to85°C -55to125°C

Min. Max. Min. Max.

2.0 2.0 V

0.8 0.8 V

IO=-100 µAVCC-0.2 VCC-0.2

=-12 mA

I

O

I

=-18 mA

O

=-24 mA

I

O

IO=100 µA

I

=12 mA

O

I

=16 mA

O

=24 mA

I

O

V

= 0 to 5.5V

I

or VO=5.5V

V

I

I=VIH

or V

V
VO= 0 to V

VI=VCCor GND

or VO= 3.6 to 5.5V

V

I

VIH=VCC-0.6V

IL

CC

2.2 2.2

2.4 2.4

2.2 2.2

0.2 0.2

0.4 0.4

0.4 0.4

0.55 0.55
± 5 ± 5 µA

10 10 µA

± 5 ± 5 µA

20 20

± 20 ± 20

500 500 µA

Unit

V

V

µA

DYNAMIC SWITCHING CHARA CTERISTICS

Test Condition Value

=25°C

Symbol Parameter

V

CC

(V)

V

OLP

V

OLV

1) Number ofoutputsdefinedas "n".Measured with "n-1"outputsswitching fromHIGH to LOW orLOW to HIGH. Theremaining outputis
measured in the LOW state.

Dynamic Low Level Quiet
Output (note 1)

3.3

=50pF

C

L

V

=0V,VIH= 3.3V

IL

4/10

T

A

Min. Typ. Max.

0.8

-0.8

Unit

V

AC ELECTRICAL C HARACTERISTICS

74LCX16373

Test Condition Value

Symbol Parameter

V

CC

(V)

t

PLHtPHL

t

PLHtPHL

t

PZLtPZH

Propagation Delay
Time (Dn to Qn)

Propagation Delay
Time (LE to Qn)

Output Enable Time
to HIGH and LOW
level

t

PLZtPHZ

Output Disable Time
from HIGH to LOW
level

t

Set-Up Time, HIGH

S

or LOW level
(DntoLE)

t

Hold Time, HIGH or

h

LOW level
(DntoLE)

t

t

OSLH

t

OSHL

1) Skew isdefined astheabsolute value ofthe difference between the actual propagation delay for any twooutputs ofthe same device switch­ing in the same direction, either HIGH or LOW (t

2) Parameter guaranteed by design

LE Pulse Width,

W

HIGH
Output To Output

Skew Time (note1,

2)

2.7

3.0 to 3.6 1.5 5.4 1.5 5.4

2.7

3.0 to 3.6 1.5 5.5 1.5 5.5

2.7

3.0 to 3.6 1.5 6.1 1.5 6.1

2.7

3.0 to 3.6 1.5 6.0 1.5 6.0

2.7

3.0 to 3.6 2.5 2.5

2.7

3.0 to 3.6 1.5 1.5

2.7

3.0 to 3.6 3.0 3.0

3.0 to 3.6 50 500 2.5 1.0 1.0 ns

OSLH

C

L

(pF)

50 500 2.5

50 500 2.5

50 500 2.5

50 500 2.5

50 500 2.5

50 500 2.5

50 500 2.5

=|t

PLHm-tPLHn

R

(Ω)

|, t

L

OSHL

t

s

(ns)

= t

=|t

-40 to 85 °C -55 to 125 °C

r

Min. Max. Min. Max.

1.5 5.9 1.5 5.9

1.5 6.4 1.5 6.4

1.5 6.5 1.5 6.5

1.5 6.3 1.5 6.3

2.5 2.5

1.5 1.5

3.0 3.0

PHLm-tPHLn

|)

Unit

ns

ns

ns

ns

ns

ns

ns

CAPACITIVE CHARACTERISTICS

Test Condition Value

=25°C

Symbol Parameter

V

CC

(V)

C

C

OUT

C

1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
circuit)

Input Capacitance

IN

Output Capacitance
Power Dissipation Capacitance

PD

(note 1)

3.3

3.3

VIN= 0 to V
VIN= 0 to V

3.3 fIN= 10MHz
V

= 0 or V

IN

CC
CC

CC

T

A

Min. Typ. Max.

7pF
8pF

20

CC(opr)=CPDxVCCxfIN+ICC

Unit

pF

/16 (per

5/10

74LCX16373

TEST CIRCUIT

TEST SWITCH

t

PLH,tPHL

t

PZL,tPLZ

t

PZH,tPHZ

CL= 50 pF or equivalent (includes jig and probe capacitance)
R

=R1=500Ω or equivalent

L

R

T=ZOUT

of pulse generator (typically 50Ω)

Open

6V

GND

WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE M INIMUM PULSE WIDTH, Dn TO LE
SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)

6/10

WAVEFORM 2 : OUTPUT ENABL E AND DISABLE TIME (f=1MHz; 50% duty cycle)

74LCX16373

WAVEFORM 3 : PROPAGATION DEL AY TIME (f=1MHz; 50% duty cycle)

7/10

74LCX16373

TSSOP48 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.006

A2 0.9 0.035

b 0.17 0.27 0.0067 0.011

c 0.09 0.20 0.0035 0.0079

D 12.4 12.6 0.488 0.496

E 8.1 BSC 0.318 BSC

E1 6.0 6.2 0.236 0.244

e 0 .5 BSC 0.0197 BSC

K0˚ 8˚0˚ 8˚

L 0.50 0.75 0. 020 0.030

A2

A

A1

b

e

D

K

c

E1

L

E

PIN 1 IDENTIFICATION

8/10

1

7065588C

74LCX16373

Tape & Reel TSSOP48 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362

T 30.4 1.197
Ao 8.7 8.9 0.343 0.350
Bo 13.1 13.3 0.516 0.524
Ko 1.5 1.7 0.059 0.067
Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

9/10

74LCX16373

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consequences of use o f suc h inf ormat ion n or f or an y infr ingeme nt of paten ts or oth er ri gh ts of third part ies whic h may resul t f rom
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
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