The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device
features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs
enter the latches. In this condition the latches are transparent, a latch output will change each time
its corresponding D-input changes. When LE is LOW the latches store the information that was
present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE
causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not
affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting
resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
•Wide supply voltage range from 2.0 to 6.0 V
•CMOS low power dissipation
•High noise immunity
•Input levels:
•For 74HC573: CMOS level
•For 74HCT573: TTL level
•Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
•Useful as input or output port for microprocessors and microcomputers
•3-state non-inverting outputs for bus-oriented applications
•Common 3-state output enable input
•Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
•Complies with JEDEC standards:
•JESD8C (2.7 V to 3.6 V)
•JESD7A (2.0 V to 6.0 V)
•ESD protection:
••HBM JESD22-A114F exceeds 2000 V
•MM JESD22-A115-A exceeds 200 V
•Multiple package options
•Specified from -40 °C to +85 °C and from -40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
PackageType number
Temperature range NameDescriptionVersion
74HC573D
74HCT573D
74HC573PW
74HCT573PW
74HC573BQ
74HCT573BQ
-40 °C to +125 °CSO20plastic small outline package; 20 leads;
-40 °C to +125 °CTSSOP20plastic thin shrink small outline package; 20 leads;
-40 °C to +125 °CDHVQFN20plastic dual in-line compatible thermal enhanced
SOT163-1
body width 7.5 mm
SOT360-1
body width 4.4 mm
SOT764-1
very thin quad flat package; no leads; 20 terminals;
body 2.5 × 4.5 × 0.85 mm
74HC_HCT573All information provided in this document is subject to legal disclaimers.
Product data sheetRev. 8 — 10 September 20213 / 16
5.2. Pin description
20supply voltage
(1) This is not a ground pin. There is no electrical or
mechanical requirement to solder the pad. In case
soldered, the solder land should remain floating or
connected to GND.
H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
Z = high-impedance OFF-state.
ControlInputOutputOperating mode
Internal latches
OELEDn
LH
(transparent mode)
LLLEnable and read register
HHH
lLLLatch and read registerLL
hHH
lLZLatch register and disable outputs HL
hHZ
7. Limiting values
Qn
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol ParameterConditionsMinMaxUnit
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1] For SOT163-1 (SO20) package: P
supply voltage-0.5+7V
input clamping currentVI < -0.5 V or VI > VCC + 0.5 V-±20mA
output clamping currentVO < -0.5 V or VO > VCC + 0.5 V-±20mA
output currentVO = -0.5 V to (VCC + 0.5 V)-±35mA
supply current-+70mA
ground current-70-mA
storage temperature-65+150°C
total power dissipation[1]-500mW
derates linearly with 12.3 mW/K above 109 °C.
For SOT360-1 (TSSOP20) package: P
For SOT764-1 (DHVQFN20) package: P
tot
derates linearly with 10.0 mW/K above 100 °C.
tot
derates linearly with 12.9 mW/K above 111 °C.
tot
8. Recommended operating conditions
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
V
CC
V
I
V
O
T
amb
supply voltage2.05.06.04.55.05.5V
input voltage0-V
output voltage0-V
ambient temperature-40+25+125-40+25+125°C
Δt/ΔVinput transition rise and fall
rate
74HC57374HCT573Symbol ParameterConditions
MinTypMaxMinTypMax
CC
CC
0-V
0-V
VCC = 2.0 V--625---ns/V
VCC = 4.5 V-1.67139-1.67139ns/V
VCC = 6.0 V--83---ns/V
CC
CC
Unit
V
V
74HC_HCT573All information provided in this document is subject to legal disclaimers.
Product data sheetRev. 8 — 10 September 20214 / 16
[1] tpd is the same as t
[2] ten is the same as t
[3] t
is the same as t
dis
[4] tt is the same as t
[5] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC 2 × fo) = sum of outputs.
THL
PLH
PZH
PLZ
and t
and t
and t
and t
TLH
PHL
PZL
PHZ
.
.
.
.
25 °C-40 °C to
+85 °C
-40 °C to
+125 °C
MinTypMaxMinMaxMinMax
Unit
10.1. Waveforms and test circuit
Measurement points are given in Table 8.
Fig. 7.Propagation delay data input (Dn) to output (Qn) and output transition time
Measurement points are given in Table 8.
Fig. 8.Pulse width latch enable input (LE), propagation delay latch enable input (LE) to output (Qn) and output
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig. 11. Test circuit for measuring switching times
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
Table 9. Test data
InputLoadS1 positionType
74HC573V
V
I
CC
tr, t
f
C
L
R
L
t
PHL
, t
PLH
t
PZH
6 ns15 pF, 50 pF 1 kΩopenGNDV
74HCT5733 V6 ns15 pF, 50 pF 1 kΩopenGNDV
, t
PHZ
t
PZL
CC
CC
, t
PLZ
74HC_HCT573All information provided in this document is subject to legal disclaimers.
Product data sheetRev. 8 — 10 September 202110 / 16
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specification.
74HC573; 74HCT573
Octal D-type transparent latch; 3-state
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74HC_HCT573All information provided in this document is subject to legal disclaimers.