Datasheet 74HCT5555N, 74HCT5555D, 74HC5555D, 74HC5555U, 74HC5555N Datasheet (Philips)

DATA SH EET

Product specification
File under Integrated Circuits, IC06

September 1993

INTEGRATED CIRCUITS

74HC/HCT5555

Programmable delay timer with
oscillator

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

September 1993 2

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

FEATURES

• Positive and negative edge
triggered

• Retriggerable or non-retriggerable

• Programmable delay

minimum: 100 ns
maximum: depends on input

frequency and division ratio

• Divide-by range of 2 to 2

24

• Direct reset terminates output
pulse

• Very low power consumption in
triggered start mode

• 3 oscillator operating modes:
– RC oscillator
– Crystal oscillator
– External oscillator

• Device is unaffected by variations
in temperature and VCC when using
an external oscillator

• Automatic power-ON reset

• Schmitt trigger action on both

trigger inputs

• Direct drive for a power transistor

• Low power consumption in active

mode with respect to TTL type
timers

• High precision due to digital timing

• Output capability: 20 mA

• ICC category: MSI.

APPLICATIONS

• Motor control

• Attic fan timers

• Delay circuits

• Automotive applications

• Precision timing

• Domestic appliances.

GENERAL DESCRIPTION

The 74HC/HCT5555 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard
no. 7A.

The 74HC/HCT5555 are precision
programmable delay timers which
consist of:

• 24-stage binary counter

• integrated oscillator (using external

timing components)

• retriggerable/non-retriggerable
monostable

• automatic power-ON reset

• output control logic

• oscillator control logic

• overriding asynchronous master

reset (MR).

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25 °C; tr = tf = 6 ns.

Notes

1. C

PD

is used to determine the dynamic power dissipation (PD in µW):

PD = CPD x V

CC

2

x fi + Σ(CL x V

CC

2

x fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
Σ(CL x V

CC

2

x fo) = sum of outputs.
CL = output load capacitance in pF
VCC = supply voltage in V

2. For HC the condition is VI = GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V.

ORDERING INFORMATION

SYMBOL PARAMETER CONDITIONS TYP. UNIT

t

PHL/tPLH

propagation delay CL = 15 pF;

VCC= 5 V

A,

B to Q/Q2424ns

MR to Q/

Q1920ns

RS to Q/

Q2628ns

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation
capacitance per buffer

notes 1 and 2 23 36 pF

EXTENDED TYPE

NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

74HC/HCT5555N 16 DIL plastic SOT38Z
74HC/HCT5555D 16 SO16 plastic SOT109A

September 1993 3

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

PINNING

SYMBOL PIN DESCRIPTION

RS 1 clock input/oscillator pin
R

TC

2 external resistor connection

C

TC

3 external capacitor connection

A 4 trigger input (positive-edge

triggered)

B 5 trigger input (negative-edge

triggered)

RTR/

RTR 6 retriggerable/non-retriggerable

input (active HIGH/active LOW)
Q 7 pulse output (active LOW)
GND 8 ground (0 V)
Q 9 pulse output (active HIGH)
S

0

− S

3

10, 11,

12, 13

programmable input

OSC CON 14 oscillator control
MR 15 master reset input (active

HIGH)
V

CC

16 positive supply voltage

Fig.1 Pin configuration.

handbook, halfpage

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

5555

GND

V

CC

MGA642

R

TC

C

TC

Q

RS

OSC
CON

MR

A
B

RTR/

RTR

Q

0

S

1

S

2

S

S

3

Fig.2 IEC logic diagram.

handbook, halfpage

MGA643

1

I = 0

S

R

R

&

CT = 0

CT = m R

V16

7

9

17

16G17

CX

RX

1
2
4
8

X / Y CTRDIVm

[T]

Y = 0

Y = 15

! G

+

0

15

10
11
12
13

2
3

14

1
6

4
5

15

September 1993 4

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Fig.3 Functional diagram.

handbook, full pagewidth

MGA644

R

TC

C

TC

MONOSTABLE

CIRCUITRY

Q

RS

OSC
CON

MR
A

B

1

14

15

4

5
6

9
7

2 3 10 11 12 13

POWER-ON

RESET

RTR/RTR

OUTPUT

STAGE

Q

24 - STAGE COUNTER

CP

CD

012

SSSS

3

FUNCTIONAL DESCRIPTION

The oscillator configuration allows the
design of RC or crystal oscillator
circuits. The device can operate from
an external clock signal applied to the
RS input (RTC and CTC must not be
connected). The oscillator frequency
is determined by the external timing
components (RT and CT), within the
frequency range 1 Hz to 4 MHz
(32 kHz to 20 MHz with crystal
oscillator).

In the HCT version the MR input is
TTL compatible but the RS input has
CMOS input switching levels. The RS
input can be driven by TTL input
levels if RS is tied to VCC via a pull-up
resistor.

The counter divides the frequency to
obtain a long pulse duration. The
24-stage is digitally programmed via
the select inputs (S0 to S3). Pin S3 can
also be used to select the test mode,
which is a convenient way of
functionally testing the counter.

The “5555” is triggered on either the
positive-edge, negative-edge or both.

• Trigger pulse applied to input A for
positive-edge triggering

• Trigger pulse applied input

B for

negative-edge triggering

• Trigger pulse applied to inputs A
and B (tied together) for both
positive-edge and negative
triggering.

The Schmitt trigger action in the
trigger inputs, transforms slowly
changing input signals into sharply
defined jitter-free output signals and
provides the circuit with excellent
noise immunity.

The OSC CON input is used to select
the oscillator mode, either
continuously running (OSC CON =
HIGH) or triggered start mode (OSC
CON = LOW). The continuously
running mode is selected where a
start-up delay is an undesirable
feature and the triggered start mode
is selected where very low power
consumption is the primary concern.

The start of the programmed time
delay occurs when output Q goes
HIGH (in the triggered start mode, the
previously disabled oscillator will
start-up). After the programmed time
delay, the flip-flop stages are reset
and the output returns to its original
state.

An internal power-on reset is used to
reset all flip-flop stages.

The output pulse can be terminated
by the asynchronous overriding
master reset (MR), this results in all
flip-flop stages being reset. The
output signal is capable of driving a
power transistor. The output time
delay is calculated using the following
formula (minimum time delay is
100 ns):

Once triggered, the output width may
be extended by retriggering the
gated, active HIGH-going input A or
the active LOW-going input

B. By
repeating this process, the output
pulse period (Q = HIGH, Q = LOW)
can be made as long as desired. This
mode is selected by RTR/RTR =
HIGH. A LOW on RTR/RTR makes,
once triggered, the outputs (Q, Q)
independent of further transitions of
inputs A and B.

1
f

i

-- -

division ratio (s).×

September 1993 5

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

dbook, full pagewidth

MGA655

RTCC

TC

Q

RS

OSC

CON

MR

A

B

RTR/

RTR

Q

0

S

1

S

2

S

S

3

CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q

CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q

CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q CP

CD

Q

CP

CD

Q

V

CC

Fig.4 Logic diagram.

September 1993 6

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

TEST MODE

Set S3 to a logic LOW level, this will divide the 24 stage counter into three, parallel clocking, 8-stage counters. Set S0,
S1 and S2 to a logic HIGH level, this programs the counter to divide-by 28 (256). Apply a trigger pulse and clock in 255
pulses, this sets all flip-flop stages to a logic HIGH level. Set S3 to a logic HIGH level, this causes the counter to divide-by

224. Clock one more pulse into the RS input, this causes a logic 0 to ripple through the counter and output Q/Q goes from
HIGH-to-LOW level. This method of testing the delay counter is faster than clocking in 224 (16 777 216) clock pulses.

FUNCTION TABLE

Notes

1. H = HIGH voltage level
L = LOW voltage level
X = don't care

↑ = LOW-to-HIGH transition
↓ = HIGH-to-LOW transition.

INPUTS OUTPUTS

MR A

BQQ

HXXLH

L↑X one HIGH level

output pulse

one LOW level

output pulse

LX↓one HIGH level

output pulse

one LOW level

output pulse

September 1993 7

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

DELAY TIME SELECTION

SELECT INPUTS OUTPUT Q/Q (FREQUENCY DIVIDING)

S

3

S

2

S

1

S

0

BINARY DECIMAL

LLLL2

1

2

LLLH2

2

4

LLHL2

3

8

LLHH2

4

16

LHLL2

5

32

LHLH2

6

64

LHHL2

7

128

LHHH2

8

256

..... .

HLLL2

17

131 072

HLLH2

18

262 144

HLHL2

19

524 288

HLHH2

20

1 048 576

HHLL2

21

2 097 152

HHLH2

22

4 194 304

HHHL2

23

8 388 608

HHHH2

24

16 777 216

Fig.5 Timing diagram.

Timing example shown for S3, S2, S1, S0 = 0011 (binary 24, decimal 16).

handbook, full pagewidth

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

RS

MR

A

Q

MGA649

September 1993 8

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.

DC CHARACTERISTICS FOR 74HC

SYM-

BOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −40 to +125

V

CC

(V)

V

I

OTHER

MIN TYP MAX MIN MAX MIN MAX

V

OH

HIGH level
output voltage
Q and Q
outputs

1.9

4.4

5.9

2

4.5

6.0

−

−

−

1.9

4.4

5.9

−

−

−

1.9

4.4

5.9

−

−

−

V
V
V

2.0

4.5

6.0

Io = −20 µA

V

OH

HIGH level
output voltage
Q and Q
outputs

3.98

5.48

4.32

5.81−−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

Io = −6.0 mA
Io = −7.8 mA

V

OH

HIGH level
output voltage
Q and Q
outputs

3.3

4.8−−

−

−

3

4.5−−

2.7

4.2−−

V
V

4.5

6.0

Io = −20 mA
Io = −20 mA

V

OL

LOW level
output voltage
Q and Q
outputs

−

−

−

0
0
0

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

V
V
V

2.0

4.5

6.0

Io = 20 µA

V

OL

LOW level
output voltage
Q and Q
outputs

−

−

0.15

0.15

0.26

0.26−−

0.33

0.33−−

0.40

0.40VV

4.5

6.0

Io = 6.0 mA
Io= 7.8 mA

V

OL

LOW level
output voltage
Q and Q
outputs

−

−

−

−

0.9

0.9−−

1.14

1.14−−

1.34

1.34VV

4.5

6.0

Io = 20 mA
Io = 25 mA

V

IH

HIGH level
input voltage
RS input

1.7

3.6

4.8

−

−

−

−

−

−

1.7

3.6

4.8

−

−

−

1.7

3.6

4.8

−

−

−

V
V
V

2

4.5

6.0

V

IL

LOW level
input voltage
RS input

−

−

−

−

−

−

0.3

0.9

1.2

−

−

−

0.3

0.9

1.2

−

−

−

0.3

0.9

1.2

V
V
V

2.0

4.5

6.0

September 1993 9

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

V

OH

HIGH level
output voltage
RTC output

3.98

5.48−−

−

−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

RS = GND;
OSC CON
= V

CC

Io = −2.6 mA
Io = −3.3 mA

3.98

5.48−−

−

−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

RS = V

CC

;
OSC CON
= GND;
untriggered

Io = −0.65 mA
Io = −0.85 mA

1.9

4.4

5.9

2.0

4.5
6

−

−

−

1.9

4.4

5.9

−

−

−

1.9

4.4

5.9

−

−

−

V
V
V

2.0

4.5

6.0

RS = V

CC

;
OSC CON
= V

CC

Io = −20 µA

1.9

4.4

5.9

2.0

4.5

6.0

−

−

−

1.9

4.4

5.9

−

−

−

1.9

4.4

5.9

−

−

−

V
V
V

2

4.5

6.0

RS = V

CC

;
OSC CON
= GND;
untriggered

Io = −20 µA

V

OH

HIGH level
output voltage
CTC output

3.98

5.48−−

−

−

3.84

5.34−−

3.7

5.2−−

V
V

4.5

6.0

RS = VIH;
OSC CON
= V

IH

Io = −3.2 mA
Io = −4.2 mA

V

OL

LOW level
output voltage
RTC output

−

−

−

−

0.26

0.26−−

0.33

0.33−−

0.4

0.4VV

4.56RS = VCC;
OSC CON
= V

CC

Io = 2.6 mA I

o

= 3.3 mA

−

−

−

0
0
0

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

−

−

−

0.1

0.1

0.1

V
V
V

2.0

4.5

6

RS = V

CC

;
OSC CON
= V

CC

Io = 20 µA

V

OL

LOW level
output voltage
CTC output

−

−

−

−

0.26

0.26−−

0.33

0.33−−

0.4

0.4VV

4.5

6.0

RS = VIL;
OSC CON
= VIL;
untriggered

Io = 3.2 mA I

o

= 4.2 mA

SYM-

BOL

PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −40 to +125

V

CC

(V)

V

I

OTHER

MIN TYP MAX MIN MAX MIN MAX

September 1993 10

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

r

= tf = 6 ns; CL = 50 pF.

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −40 to +125

V

CC

(V)

WAVEFORMS

MIN TYP MAX MIN MAX MIN MAX

t

PLH/tPHL

propagation
delay A, B to
Q, Q

−

−

−

77
28
22

240
48
41

−

−

−

300
60
51

−

−

−

360
72
61

ns
ns
ns

2.0

4.5

6.0

Fig.6

t

PLH/tPHL

propagation
delay MR to Q,
Q

−

−

−

61
22
18

185
37
31

−

−

−

230
46
39

−

−

−

280
56
48

ns
ns
ns

2.0

4.5

6.0

Fig.7

t

PLH/tPHL

propagation
delay RS to Q,
Q

−

−

−

83
30
24

250
50
43

−

−

−

315
63
54

−

−

−

375
75
64

ns
ns
ns

2.0

4.5

6.0

Fig.8; note 1

t

THL/tTLH

output
transition time−−

−

19
7
6

75
15
13

−

−

−

95
19
16

−

−

−

110
22
19

ns
ns
ns

2.0

4.5

6.0

Fig.6

t

W

trigger pulse
width
A = HIGH

B = LOW

70
14
12

17
6
5

−

−

−

90
18
15

−

−

−

105
21
18

−

−

−

ns
ns
ns

2.0

4.5

6.0

Fig.6

t

W

master reset
pulse width
HIGH

70
14
12

19
7
6

−

−

−

90
18
15

− 105
21
18

−

−

−

ns
ns
ns

2.0

4.5

6.0

Fig.7

t

W

clock pulse
width RS;
HIGH or LOW

80
16
14

25
9
7

−

−

−

100
20
17

−

−

−

120
24
20

−

−

−

ns
ns
ns

2.0

4.5

6.0

Fig.8

t

W

minimum
output pulse
width
Q = HIGH,
Q = LOW

−

−

−

275
100
80

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

ns
ns
ns

2.0

4.5

6.0

Fig.6; note 1

t

rt

retrigger time
A, B

−

−

−

0
0
0

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

ns
ns
ns

2.0

4.5

6.0

Fig.10; note 2

R

EXT

external timing
resistor

5
1

−

−

1000
1000−−

−

−

−

−

−

−

−

−

kΩkΩ2.0

5.0

Fig.13

C

EXT

external timing
capacitor

50
50

no limits

pFpF2.0

5.0

Fig.13

t

rem

removal time
MR to A, B

120
24
20

39
14
11

−

−

−

150
30
26

−

−

−

180
36
31

−

−

−

ns
ns
ns

2.0

4.5

6.0

Fig.7

September 1993 11

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Notes

1. One stage selected.

2. It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period
exceeds the clock input cycle time divided by 2.

3. One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the
RS clock input.

4. One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of
the RS clock input.

f

max

maximum
clock pulse
frequency

2
10
12

5.9
18
21

−

−

−

1.8
8
10

−

−

−

1.3

6.6
8

−

−

−

MHz
MHz
MHz

2.0

4.5

6.0

Fig.8; note 3

f

max

maximum
clock pulse
frequency

6
30
35

24.8
75
89

−

−

−

4.8
24
28

−

−

−

4
20
24

−

−

−

MHz
MHz
MHz

2.0

4.5

6.0

Fig.9; note 4

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −40 to +125

V

CC

(V)

WAVEFORMS

MIN TYP MAX MIN MAX MIN MAX

September 1993 12

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: non-standard; bus driver with extended specification on VOH and V

OL

ICC category: MSI.

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −0to+125

V

CC

(V)

V

I

OTHER

MIN TYP MAX MIN MAX MIN MAX

V

OH

HIGH level
output voltage
Q and Q
outputs

4.4 4.5 − 4.4 − 4.4 − V 4.5 Io = −20 µA

V

OH

HIGH level
output voltage
Q and Q
outputs

3.98 4.32 − 3.84 − 3.7 − V 4.5 Io = −6 mA

V

OH

HIGH level
output voltage
Q and Q
outputs

3.3 −− 3− 2.7 − V 4.5 Io = −20 mA

V

OL

LOW level
output voltage
Q and Q
outputs

− 0 0.1 − 0.1 − 0.1 V 4.5 Io = 20 µA

V

OL

LOW level
output voltage
Q and Q
outputs

− 0.15 0.26 − 0.33 − 0.40 V 4.5 Io = 6 mA

V

OL

LOW level
output voltage
Q and Q
outputs

−−0.9 − 1.14 − 1.34 V 4.5 − Io = 20 mA

September 1993 13

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Notes

1. The RS input has CMOS input switching levels.

2. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To
determine ∆ICC per input, multiply this value by the unit load coefficient shown in the following table.

UNIT LOAD COEFFICIENT

V

OH

HIGH level
output
voltage R

TC

output

3.98 −− 3.84 − 3.7 − V 4.5 RS = GND;
OSC CON
=V

CC

Io = −2.6 mA

3.98 −− 3.84 − 3.7 − V 4.5 RS = V

CC

;
OSC CON
= GND;
untriggered

Io =

−0.65 mA

4.4 4.5 − 4.4 − 4.4 − V 4.5 RS = V

CC

;
OSC CON
= V

CC

Io = −20 µA

4.4 4.5 − 4.4 − 4.4 − V 4.5 RS = V

CC

;
OSC CON
= GND;
untriggered

Io = −20 µA

V

OH

HIGH level
output
voltage C

TC

output

3.98 −− 3.84 − 3.7 − V 4.5

RS = VIH;
OSC CON
= V

IH

Io = −3.2 mA

V

OL

LOW level
output
voltage R

TC

output

−−0.26 − 0.33 − 0.4 V 4.5

RS = V

CC

;
OSC CON
= V

CC

Io = 2.6 mA

− 0 0.1 − 0.1 − 0.1 V 4.5

RS = V

CC

;
OSC CON
= V

CC

Io = 20 µA

V

OL

LOW level
output
voltage C

TC

output

−−0.26 − 0.33 − 0.4 V 4.5

RS = VIL;
OSC CON
= VIL;
untriggered

Io = 3.2 mA

INPUT UNIT LOAD COEFFICIENT

MR 0.35

A 0.69
B 0.50

RTR/

RTR 0.35

OSC CON 1.20

S0 - S

2

0.65

S

3

0.40

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −0to+125

V

CC

(V)

V

I

OTHER

MIN TYP MAX MIN MAX MIN MAX

September 1993 14

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

r

= tf = 6 ns; CL = 50 pF.

SYMBOL PARAMETER

T

amb

(°C)

UNIT

TEST CONDITION

+25 −40 to +85 −40 to +125

V

CC

(V)

WAVEFORMS

MIN TYP MAX MIN MAX MIN MAX

t

PLH/tPHL

propagation
delay A, B to
Q, Q

− 28 48 − 60 − 72 ns 4.5 Fig.6

t

PHL/tPLH

propagation
delay MR to Q,
Q

− 24 41 − 51 − 62 ns 4.5 Fig.7

t

PHL/tPLH

propagation
delay RS to Q,
Q

− 32 54 − 68 − 81 ns 4.5 Fig.8; note 1

t

THL/tTLH

output
transition time

− 715−19 − 22 ns 4.5 Fig.6

t

W

trigger pulse
width
A = HIGH
B = LOW

21 12 − 26 − 32 − ns 4.5 Fig.6

t

W

master reset
pulse width
HIGH

14 5 − 18 − 21 − ns 4.5 Fig.7

t

W

clock pulse
width RS;
HIGH or LOW

16 9 − 20 − 24 − ns 4.5 Fig.8

t

W

minimum
output pulse
width
Q = HIGH,
Q = LOW

− 100 −−−−−ns 4.5 Fig.6

t

rt

retrigger time
A, B

− 0 −−−−−ns 4.5 Fig.10; note 2

R

EXT

external timing
resistor

1 − 1000 −−−−kΩ4.5 Fig.13

C

EXT

external timing
capacitor

50 no limits pF 4.5 Fig.13

t

rem

removal time
MR to A, B

24 14 − 30 − 36 − ns 4.5 Fig.7

f

max

maximum
clock pulse
frequency

10 18 − 8 − 6.6 − MHz 4.5 Fig.8; note 3

f

max

maximum
clock pulse
frequency

30 75 − 24 − 20 − MHz 4.5 Fig.9; note 4

September 1993 15

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Notes

1. One stage selected.

2. It is possible to retrigger directly after the trigger pulse, however the pulse will only be extended, if the time period
exceeds the clock input cycle time divided by 2.

3. One stage selected. The termination of the output pulse remains synchronized with respect to the falling edge of the
RS clock input.

4. One stage selected. The termination of the output pulse is no longer synchronized with respect to the falling edge of
the RS clock input.

September 1993 16

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

AC WAVEFORMS

Fig.6 Waveforms showing the triggering of the delay timer by input A or B, the minimum pulse widths of the

trigger inputs A and B, the output pulse width and output transition times.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

handbook, full pagewidth

t

W

Q OUTPUT

MGA653

Q OUTPUT

90%

10%

A INPUT

B INPUT

V

M

(1)

V

M

(1)

t

TLH

t

THL

90%

10%

t

W

GND

V

M

(1)

90%

10%

t

W

90%

10%

t

PHL

t

PLH

V

M

(1)

t

TLH

t

THL

September 1993 17

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Fig.7 Waveforms showing the master reset (MR) pulse width, the master reset to outputs (Q and Q) propagation

delays and the master reset to trigger inputs (A and B) removal time.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

handbook, full pagewidth

t

PHL

V

M

(1)

t

W

t

PLH

Q OUTPUT

MR INPUT

MGA652-1

V

M

(1)

Q OUTPUT

t

rem

A INPUT

B INPUT

V

M

(1)

V

M

(1)

V

M

(1)

t

rem

September 1993 18

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Fig.8 Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and

the maximum clock frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

handbook, full pagewidth

t

PHL

V

M

(1)

t

W

t

PLH

Q OUTPUT

RS INPUT

MGA651

V

CC

1

2

V

M

(1)

Q OUTPUT

1/f max

Fig.9 Waveforms showing the clock (RS) to outputs (Q and Q) propagation delays, the clock pulse width and

the maximum clock frequency (Output waveforms are not synchronized with respect to the RS waveform).

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

handbook, full pagewidth

t

PHL

V

M

(1)

1/f max

t

PLH

Q OUTPUT

RS INPUT

MGA654

V

M

(1)

Q OUTPUT

V

M

(1)

September 1993 19

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Fig.10 Output pulse control using retrigger pulse (RTR/RTR = HIGH).

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

M

= 1.3 V; VI= GND to 3 V.

handbook, full pagewidth

A INPUT

Q OUTPUT

B INPUT

t

W

t

rt

t

W

t

W

t

W

t

W

MGA650

September 1993 20

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

APPLICATION INFORMATION

Fig.11 Test set-up for measuring forward

transconductance gfs = dio/dvi at vo is
constant (see Fig.12) and MR = LOW.

handbook, halfpage

MGA645

A

output

100 F

V

CC

input

0.47 F

R = 560 kΩ

bias

i

o

(f = 1 kHz)

GND

v

i

µ

µ

Fig.12 Typical forward transconductance gfs as a

function of the supply voltage at VCC at
T

amb

= 25 °C.

handbook, halfpage

MBA333

14

12

10

8

6

4

2

0123456

g

fs

(mA/V)

CC

V

(V)

max.

min.

typ.

Fig.13 Application information.

Ct curve at Rt = 100 kΩ; R2 = 200 kΩ.
Rt curve at Ct = 1 nF; R2 = 2 x Rt.
RC oscillator frequency as a function of Rt and C

t

at VCC = 2 to 6 V; T

amb

= 25 °C.

handbook, halfpage

10

3

MGA647

10

4

10

5

10

6

10

10

5

10

3

10

4

10

2

f

osc

(Hz)

R ( )

t

C ( F)

t

10

–4

10

–3

10

–2

10

–1

R

t

C

t

Ω
µ

Fig.14 Example of an RC oscillator.

Typical formula for oscillator frequency:

f

osc

1

2.5 RtCt××

--------------------------------

=

handbook, halfpage

MGA646

2

RS1

MR (from logic)

R

TC

C

TC

3

R

t

C

t

C2 R2

September 1993 21

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Timing Component Limitations

The oscillator frequency is mainly
determined by RtCt, provided R2 ≈
2Rt and R2C2 << RtCt. The function
of R2 is to minimize the influence of
the forward voltage across the input
protection diodes on the frequency.
The stray capacitance C2 should be
kept as small as possible. In
consideration of accuracy, Ct must be
larger than the inherent stray
capacitance. Rt must be larger than
the “ON” resistance in series with it,
which typically is 280 Ω at
VCC= 2 V, 130 Ω at VCC = 4.5 V and
100 Ω at VCC = 6 V. The
recommended values for these
components to maintain agreement
with the typical oscillation formula are:

Ct> 50 pF, up to any practical value,
10 kΩ< Rt< 1 MΩ.

In order to avoid start-up problems,
Rt>> 1 kΩ.

Typical Crystal Oscillator

In Fig.15, R2 is the power limiting
resistor. For starting and maintaining
oscillation a minimum
transconductance is necessary, so
R2 should not be too large. A practical
value for R2 is 2.2 kΩ. Above 14 MHz
it is recommended replacement of R2
by a capacitor with a typical value of
35 pF.

Accuracy

Device accuracy is very precise for
long time delays and has an accuracy
of better than 1% for short time delays
(1% applies to values ≥ 400 ns).
Tolerances are dependent on the
external components used, either RC
network or crystal oscillator.

Start-up Using External Clock

The start of the timing pulse is
initiated directly by the trigger pulse
(asynchronously with respect to the
oscillator clock). Triggering on a clock
HIGH or clock LOW results in the
following:

• clock = HIGH; the timing pulse may
be lengthened by a maximum of
tW/2 (tW = clock pulse width)

• clock = LOW; the timing pulse may
be shortened by a maximum of tW/2
(tW = clock pulse width).

This effect can be minimized by
selecting more delay stages. When
using only one or two delay stages, it
is recommended to use an external
time base that is synchronized with
the negative-edge of the clock.

Start-up Using RC Oscillator

The first clock cycle is ≈35% of a time
period too long. This effect can also
be minimized by selecting more delay
stages.

Start-up Using Crystal Oscillator

A crystal oscillator requires at least
two clock cycles to start-up plus an
unspecified period (ms) before the
amplitude of the clock signal
increases to its expected level.
Although this device also operates at
lower clock amplitudes, it is
recommended to select the
continuously running mode
(OSC CON = HIGH) to prevent
start-up delays.

Termination of the Timing Pulse

The end of the timing pulse is
synchronized with the falling edge of
the oscillator clock. The timing pulse
may lose synchronization under the
following conditions:

• high clock frequency and large
number of stages are selected.
This depends on the dynamic
relationship that exists between the
clock frequency and the ripple
through delay of the subsequent
stages.

Synchronization

When frequencies higher than those
specified in the Table
'Synchronization limits' are used, the
termination of timing pulse will lose
synchronization with the falling edge
of the oscillator. The unsynchronized
timing pulse introduces errors, which
can be minimized by increasing the
number of stages used e.g. a 20 MHz
clock frequency using all 24 stages
will result in a frequency division of
16 777 225 instead of 16 777 216, an
error of 0.0005%.

The amount of error increases at high
clock frequencies as the number of
stages decrease. A clock frequency
of 40 MHz and 4 stages selected
results in a division of 18 instead of
16, a 12.5% error. Application
example:

• If a 400 ns timing pulse was
required it would be more accurate
to utilize a 5 MHz clock frequency
using 1 stage or a 10 MHz clock
frequency using 2 stages (due to
synchronization with falling edge of
the oscillator) than a 40 MHz clock
frequency and 4 stages
(synchronization is lost).

September 1993 22

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

Minimum Output Pulse Width

The minimum output pulse width is
determined by the minimum clock
pulse width, plus the maximum
propagation delay of A, B to Q. The
rising edge of Q is dominated by the
A,B to Q propagation delay, while the
falling edge of Q is dominated by RS
to Q propagation delay. These
propagation delays are not equal. The

RS to Q propagation delay is some
what longer, resulting in inaccurate
outputs for extremely short pulses.
The propagation delays are listed in
the section 'AC Characteristics'. With
these numbers it is possible to
calculate the maximum deviation (an
example is shown in Fig.16).
Figure 16 is valid for an external clock
where the trigger is synchronized to
the falling edge of the clock only. The

graph shows that the minimum
programmed pulse width of 100 ns is:

• minimum of 4% too long

• typically 7% too long

• maximum of 10% too long.

SYNCHRONIZATION LIMITS

NUMBER OF STAGES SELECTED CLOCK FREQUENCY (TYPICAL)

1 18 MHz
2 14 MHz
3 11 MHz
4 9.6 MHz
5 8.3 MHz
6 7.3 MHz
7 6.6 MHz
8 6 MHz
..
17 3.2 MHz
18 3.0 MHz
19 2.9 MHz
20 2.8 MHz
21 2.7 MHz
22 2.6 MHz
23 2.5 MHz
24 2.4 MHz

September 1993 23

Philips Semiconductors Product specification

Programmable delay timer with oscillator 74HC/HCT5555

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

Fig.15 External components configuration for a crystal oscillator.

handbook, halfpage

MLB336

2

RS1

MR (from logic)

R

TC

R2

2.2 kΩ

C3

R

bias

100 kΩ to 1 M Ω

22 to
37 pF

C2 100 pF

Fig.16 Graphic representation of short time delay accuracy; one stage selected; VCC = 4.5 V.

handbook, full pagewidth

600

40

0

0 200 300

MGA648

100 500400

8

16

24

32

4

12

20

28

36

programmed time (ns)

deviation (%)

max. expected
typ. expected

min. expected