Page 1
DATA SH EET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Apr 10
INTEGRATED CIRCUITS
74HC/HCT534
Octal D-type flip-flop; positive
edge-trigger; 3-state; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
1998 Apr 10 2
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive, edge-triggered register
• Common 3-state output enable input
• Output capability: bus driver
• ICC category: MSI.
GENERAL DESCRIPTION
The 74HC/HCT534 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT534 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable (
OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition. When OE is LOW, the
contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “534” is functionally identical to the “374”, but has
inverted outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf=6ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD=CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz.
fo= output frequency in MHz.
∑ (CL× V
CC
2
× fo) = sum of outputs.
CL= output load capacitance in pF.
VCC= supply voltage in V.
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V.
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CP to Q
n
CL= 15 pF; VCC=5V 12 13 ns
f
max
maximum clock frequency 61 40 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2 19 19 pF
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
74HC534 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HC534 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
74HCT534 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74HCT534 DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
Page 3
1998 Apr 10 3
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
OE 3-state output enable input (active LOW)
2, 5, 6, 9, 12, 15, 16, 19
Q0to Q
7
3-state outputs
3, 4, 7, 8, 13, 14, 17, 18 D
0
to D
7
data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
20 V
CC
positive supply voltage
Fig.1 Pin configuration.
page
OE
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND
V
CC
Q
7
D
7
D
6
Q
5
D
5
Q
6
D
4
Q
4
CP
1
2
3
4
5
6
7
8
9
10
11
12
20
19
18
17
16
15
14
13
534
MGM954
Fig.2 Logic symbol.
age
MGM955
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
OE
CP
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.3 IEC logic symbol.
page
MGM956
19
16
15
12
9
6
5
11
C1
1
EN
1D
2
18
17
14
13
8
7
4
3
Page 4
1998 Apr 10 4
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
FUNCTION TABLE
Note
1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level; I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
Z = high impedance OFF-state; ↑ = LOW-to-HIGH clock transition.
OPERATING MODES
INPUTS
INTERNAL FLIP-FLOPS
OUTPUTS
OE CP D
n
Q0to Q
7
load and read register L ↑ lL H
L↑hH L
load register and disable outputs H ↑ lL Z
H↑hH Z
Fig.4 Functional diagram.
handbook, halfpage
MGM957
3-STATE
OUTPUTS
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
19
16
15
12
9
6
5
2
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
OE
FF1
to
FF8
18
11
1
17
14
13
8
7
4
3
Page 5
1998 Apr 10 5
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
Fig.5 Logic diagram.
handbook, full pagewidth
MGM958
Q
5
D
5
DCPQ
FF
6
Q
4
D
4
DCPQ
FF
5
Q
3
D
3
DCPQ
FF
4
Q
2
D
2
DCPQ
FF
3
Q
1
D
1
DCPQ
FF
2
Q
0
OE
CP
D
0
DCPQ
FF
1
Q
6
D
6
DCPQ
FF
7
Q
7
D
7
DCPQ
FF
8
Page 6
1998 Apr 10 6
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver ICCcategory: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL=50pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ
n
41 165 205 250 ns 2.0 Fig.6
15 33 41 50 4.5
12 28 35 43 6.0
t
PZH
/ t
PZL
3-state output enable
time
OE to Q
n
33 150 190 225 ns 2.0 Fig.7
12 30 38 45 4.5
10 26 33 38 6.0
t
PHZ
/ t
PLZ
3-state output disable
time
OE to Q
n
41 150 190 225 ns 2.0 Fig.7
15 30 38 45 4.5
12 26 33 38 6.0
t
THL
/ t
TLH
output transition time 14 60 75 90 ns 2.0 Fig.6
5 12 15 18 4.5
4 10 13 15 6.0
t
W
clock pulse width
HIGH or LOW
80 19 100 120 ns 2.0 Fig.6
16 7 20 24 4.5
14 6 17 20 6.0
t
su
set-up time
Dnto CP
60 6 75 90 ns 2.0 Fig.8
12 2 15 18 4.5
10 2 13 15 6.0
t
h
hold time
Dnto CP
5 −3 5 5 ns 2.0 Fig.8
5 −1 5 5 4.5
5 −1 5 5 6.0
f
max
maximum clock pulse
frequency
6.0 18 4.8 4.0 MHz 2.0 Fig.6
30 55 24 20 4.5
35 66 28 24 6.0
Page 7
1998 Apr 10 7
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver ICCcategory: MSI.
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL=50pF
INPUT UNIT LOAD COEFFICIENT
OE 1.25
CP 0.90
D
n
0.35
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
16 30 38 45 ns 4.5 Fig.6
t
PZH
/ t
PZL
3-state output enable time
OE to Q
n
16 30 38 45 ns 4.5 Fig.7
t
PHZ
/ t
PLZ
3-state output disable
time OE to Q
n
18 30 38 45 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 5 12 15 18 ns 4.5 Fig.6
t
W
clock pulse width
HIGH or LOW
23 14 29 35 ns 4.5 Fig.6
t
su
set-up time
Dnto CP
12 4 15 18 ns 4.5 Fig.8
t
h
hold time
Dnto CP
5 −1 5 5 ns 4.5 Fig.8
f
max
maximum clock pulse
frequency
22 36 18 15 MHz 4.5 Fig.6
Page 8
1998 Apr 10 8
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output
transition times and the maximum clock pulse frequency.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3V.
book, full pagewidth
MGM959
t
PHL
1/f
max
t
PLH
t
W
V
M
(1)
V
M
(1)
CP INPUT
Qn OUTPUT
t
THL
t
TLH
Fig.7 Waveforms showing the 3-state enable and disable times.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3V.
ndbook, full pagewidth
MGM961
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
90%
10%
outputs
enabled
OE INPUT
V
M
(1)
t
PZL
t
PZH
V
M
(1)
V
M
(1)
Qn OUTPUT
LOW-to-OFF
OFF-to-LOW
Qn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
t
r
t
f
90%
10%
Page 9
1998 Apr 10 9
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
Fig.8 Waveforms showing the data set-up and hold times for Dninput.
The shaded areas indicate when the input is permitted to change for predictable output performance.
(1) HC: VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3V.
handbook, full pagewidth
MGM960
t
h
t
su
t
h
t
su
Qn OUTPUT
CP INPUT
Dn INPUT
V
M
(1)
V
M
(1)
V
M
(1)
Page 10
1998 Apr 10 10
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
PACKAGE OUTLINES
UNIT
A
max.
1 2
b
1
cD E e M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT146-1
92-11-17
95-05-24
A
min.
A
max.
b
Z
max.
w
M
E
e
1
1.73
1.30
0.53
0.38
0.36
0.23
26.92
26.54
6.40
6.22
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
2.04.2 0.51 3.2
0.068
0.051
0.021
0.015
0.014
0.009
1.060
1.045
0.25
0.24
0.14
0.12
0.010.10 0.30
0.32
0.31
0.39
0.33
0.0780.17 0.020 0.13
SC603
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
20
1
11
10
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1)
(1) (1)
DIP20: plastic dual in-line package; 20 leads (300 mil)
SOT146-1
Page 11
1998 Apr 10 11
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
UNIT
A
max.
A
1
A2A3b
p
cD
(1)E(1) (1)
eHELLpQ
Z
ywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
2.65
0.30
0.10
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.1
1.0
0.9
0.4
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.1
0.4
SOT163-1
10
20
w M
b
p
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013AC
pin 1 index
0.10
0.012
0.004
0.096
0.089
0.019
0.014
0.013
0.009
0.51
0.49
0.30
0.29
0.050
1.4
0.055
0.419
0.394
0.043
0.039
0.035
0.016
0.01
0.25
0.01
0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A
1
A
2
H
E
L
p
Q
E
c
L
v M
A
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
95-01-24
97-05-22
Page 12
1998 Apr 10 12
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO
packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
W
AVE SOLDERING
Wave soldering techniques can be used for all SO
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
• The package footprint must incorporate solder thieves at
the downstream end.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Page 13
1998 Apr 10 13
Philips Semiconductors Product specification
Octal D-type flip-flop; positive edge-trigger;
3-state; inverting
74HC/HCT534
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
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