Datasheet 74HCT4514U, 74HCT4514PW, 74HCT4514N3, 74HCT4514N, 74HCT4514DB Datasheet (Philips)
...Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT4514
4-to-16 line decoder/demultiplexer
with input latches
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
September 1993 2
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
FEATURES
• Non-inverting outputs
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4514 are high-speed Si-gate CMOS
devices and are pin compatible with “4514” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4514 are 4-to-16 line
decoders/demultiplexers having four binary weighted
address inputs (A
0
to A3), with latches, a latch enable input
(LE), and an active LOW enable input (E). The 16 outputs
(Q0to Q15) are mutually exclusive active HIGH. When LE
is HIGH, the selected output is determined by the data on
An. When LE goes LOW, the last data present at Anare
stored in the latches and the outputs remain stable. When
E is LOW, the selected output, determined by the contents
of the latch, is HIGH. At E HIGH, all outputs are LOW. The
enable input (E) does not affect the state of the latch.
When the “4514” is used as a demultiplexer, E is the data
input and A0to A3are the address inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay An to Q
n
CL= 15 pF; VCC=5 V 23 26 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 44 45 pF
Page 3
September 1993 3
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1 LE latch enable input (active HIGH)
2, 3, 21, 22 A
0
to A
3
address inputs
11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14, 13, 16, 15 Q
0
to Q
15
multiplexer outputs (active HIGH)
12 GND ground (0 V)
23
E enable input (active LOW)
24 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
September 1993 4
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
Fig.4 Functional diagram.
APPLICATIONS
• Digital multiplexing
• Address decoding
• Hexadecimal/BCD decoding
FUNCTION TABLE
Notes
1. LE = HIGH
H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS
EA0A1A2A3Q0Q1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q12Q13Q14Q
15
HXXXXLLLLLLLLLLLLLLLL
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
L
L
L
L
H
Page 5
September 1993 5
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
Fig.5 Logic diagram.
Page 6
September 1993 6
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
An to Q
n
74
27
22
230
46
39
290
58
49
345
69
59
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
74
27
22
230
46
39
290
58
49
345
69
59
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
E to Q
n
41
15
12
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.6
t
W
latch enable pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
su
set-up time
Anto LE
90
18
15
25
9
7
115
23
20
135
27
23
ns 2.0
4.5
6.0
Fig.7
t
h
hold time
Anto LE
1
1
1
−11
−4
−3
1
1
1
1
1
1
ns 2.0
4.5
6.0
Fig.7
Page 7
September 1993 7
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
A
n
LE
E
0.65
1.40
1.00
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
An to Q
n
30 55 69 83 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
29 50 63 75 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
E to Q
n
17 40 50 60 ns 4.5 Fig.6
t
THL
/ t
TLH
output transition time
7 15 19 22 ns 4.5 Fig.6
t
W
latch enable pulse width
HIGH
16 4 20 24 ns 4.5 Fig.7
t
su
set-up time
Anto LE
18 9 23 27 ns 4.5 Fig.7
t
h
hold time
Anto LE
3 −3 3 3 ns 4.5 Fig.7
Page 8
September 1993 8
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
AC WAVEFORMS
Fig.6 Waveforms showing the input (An, LE, E) to output (Qn) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the minimum pulse width of the latch enable input (LE) and the set-up and hold times
for LE to An. Set-up and hold times are shown as positive values but may be specified as negative values.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Page 9
September 1993 9
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer with
input latches
74HC/HCT4514
APPLICATION INFORMATION
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.8 Code-to-code conversion; hexadecimal to BCD.
Loading...