Datasheet 74 hct4094 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4094

8-stage shift-and-store bus register

Product speciﬁcation File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

FEATURES

• Output capability: standard

• ICC category: MSI

The data in each shift register stage is transferred to the storage register when the strobe input (STR) is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) signal is HIGH.

Two serial outputs (QS1and QS2) are available for

GENERAL DESCRIPTION

The 74HC/HCT4094 are high-speed Si-gate CMOS devices and are pin compatible with the “4094” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

cascading a number of “4094” devices. Data is available at QS1on the positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at QS2on the next negative-going clock edge and is for cascading “4094” devices when the clock rise time is slow.

The 74HC/HCT4094 are 8-stage serial shift registers having a storage latch associated with each stage for strobing data from the serial input (D) to the parallel buffered 3-state outputs (QP

to QP7). The parallel outputs

0

may be connected directly to common bus lines. Data is shifted on the positive-going clock (CP) transitions.

APPLICATIONS

• Serial-to-parallel data conversion

• Remote control holding register

QUICK REFERENCE DATA

GND = 0 V; T

= 25 °C; tr= tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

f

max

C C

I PD

/ t

PLH

propagation delay CL= 15 pF; VCC= 5 V CP to QS CP to QS CP to QP STR to QP

1 2 n

n

maximum clock frequency 95 86 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 83 92 pF

TYPICAL

UNIT

HC HCT

15 19 ns 13 18 ns 20 21 ns 18 19 ns

Notes

1. C

is used to determine the dynamic power dissipation (PDin µW):

PD

PD= CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

December 1990 2

.

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 STR strobe input 2 D serial input 3 CP clock input 4, 5, 6, 7,14, 13, 12, 11 QP 8 GND ground (0 V) 9, 10 QS 15 OE output enable input 16 V

CC

to QP

0

,QS

1

parallel outputs

7

serial outputs

2

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

Fig.4 Functional diagram.

Fig.5 Logic diagram.

December 1990 4

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

FUNCTION TABLE

INPUTS PARALLEL OUTPUTS

CP OE STR D QP

↑ ↓ ↑ ↑ ↑ ↓

L

L H H H H

X X L H H H

X X X L H H

Notes

1. H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state NC= no change

↑ = LOW-to-HIGH CP transition ↓ = HIGH-to-LOW CP transition

= the information in the seventh register stage is transferred to the 8th register stage and QSnoutput at the

Q’

6

positive clock edge

Z Z

NC

L H

NC

SERIAL

OUTPUTS

0

QP

n

Z Z

NC

QP

n - 1

QP

n - 1

NC

QS

Q’ NC Q’ Q’ Q’ NC

1

6

6 6 6

QS

NC

QP

NC NC NC

QP

2

7

Fig.6 Timing diagram.

December 1990 5

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard ICCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; tr= tf= 6 ns; CL= 50 pF

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

PHL

t

PZH

t

PHZ

t

THL

t

W

/ t

propagation delay

PLH

CP to QS

propagation delay

PLH

CP to QS

propagation delay

PLH

CP to QP

propagation delay

PLH

STR to QP

3-state output enable time

PZL

OE to QP

3-state output disable

PLZ

time OE to QP

output transition time 19

TLH

1

2

n

clock pulse width

HIGH or LOW

t

W

strobe pulse width

HIGH

t

su

set-up time

D to CP

t

su

set-up time

CP to STR

(°C)

T

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

50

80 16 14

50 10 9

100 20 17

18 14

44 16 13

63 23 18

58 21 17

55 20 16

41 15 12

7 6

14 5 4

28 10 8

150 30 26

135 27 23

195 39 33

180 36 31

175 35 30

125 25 21

75 15 13

100 20 17

65 13 11

125 25 21

190 38 33

170 34 29

245 49 42

225 45 38

220 44 37

155 31 26

95 19 16

225 45 38

205 41 35

295 59 50

270 54 46

265 53 45

190 38 32

110 22 19

120 24 20

75 15 13

150 30 26

.

UNIT

ns 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.7

4.5

6.0 Fig.7

4.5

6.0 Fig.7

4.5

6.0 Fig.8

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0 Fig.7

4.5

Fig.7

4.5

6.0 Fig.8

4.5

6.0 Fig.10

4.5

6.0 Fig.8

4.5

6.0

December 1990 6

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

T

SYMBOL PARAMETER

t

h

hold time

D to CP

t

h

hold time

CP to STR

f

max

maximum clock pulse

frequency

(°C)

amb

74HC

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

3 3 3

0 0 0

6.0 30 35

−6

−2

−14

−5

−4

28 87 103

3 3 3

0 0 0

4.8 24 28

3 3 3

0 0 0

4.0 20 24

UNIT

ns 2.0

MHz 2.0

TEST CONDITIONS

WAVEFORMS

V

CC

(V)

Fig.10

4.5

6.0 Fig.8

4.5

6.0 Fig.7

4.5

6.0

December 1990 7

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see Output capability: standard

ICCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆I To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

OE, CP D STR

1.50

0.40

1.00

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

) for a unit load of 1 is given in the family specifications.

CC

.

December 1990 8

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= tf= 6 ns; CL= 50 pF

r

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

PHL

t

PZH

t

PHZ

t

THL

t

W

/ t

propagation delay

PLH

CP to QS

propagation delay

PLH

CP to QS

propagation delay

PLH

CP to QP

propagation delay

PLH

STR to QP

3-state output enable time

PZL

OE to QP

3-state output disable time

PLZ

OE to QP

output transition time 7 15 19 22 ns 4.5 Fig.7

TLH

1

2

n

clock pulse width

HIGH or LOW

t

W

strobe pulse width

HIGH

t

su

set-up time

D to CP

t

su

set-up time

CP to STR

t

h

hold time

D to CP

t

h

hold time

CP to STR

f

max

maximum clock pulse

frequency

T

amb

(°C)

TEST CONDITIONS

74HCT

+25 −40 to +85 −40 to +125

UNIT

WAVEFORMS

V

CC

(V)

min. typ. max. min. max. min. max.

23 39 49 59 ns 4.5 Fig.7

21 36 45 54 ns 4.5 Fig.7

25 43 54 65 ns 4.5 Fig.7

22 39 49 59 ns 4.5 Fig.8

20 35 44 53 ns 4.5 Fig.9

21 35 44 53 ns 4.5 Fig.9

16 7 20 24 ns 4.5 Fig.7

16 5 20 24 ns 4.5 Fig.8

10 4 13 15 ns 4.5 Fig.10

20 9 25 30 ns 4.5 Fig.8

4 0 4 4 ns 4.5 Fig.10

0 −4 0 0 ns 4.5 Fig.8

30 80 24 20 MHz 4.5 Fig.7

December 1990 9

Philips Semiconductors Product speciﬁcation

8-stage shift-and-store bus register 74HC/HCT4094

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.7 Waveforms showing the clock (CP) to

output (QPn,QS1,QS2) propagation delays, the clock pulse width and the maximum clock frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.8 Waveforms showing the strobe (STR) to

output (QPn) propagation delays and the strobe pulse width and the clock set-up and hold times for the strobe input.

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

HCT: V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

M

(1) HC : VM= 50%; VI= GND to VCC.

HCT: V

= 1.3 V; VI= GND to 3 V.

M

Fig.9 Waveforms showing the 3-state enable and

disable times for input OE.

December 1990 10

Fig.10 Waveforms showing the data set-up and

hold times for the data input (D).

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.