Datasheet 74HCT4075U, 74HCT4075PW, 74HCT4075N, 74HCT4075DB, 74HCT4075D Datasheet (Philips)
...Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4075
Triple 3-input OR gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Triple 3-input OR gate 74HC/HCT4075
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT4075 are high-speed Si-gate CMOS
devices and are pin compatible with the “4075” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT4075 provide the 3-input OR function.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay nA, nB, nC to nY CL= 15 pF; VCC= 5 V 8 10 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per gate notes 1 and 2 28 32 pF
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December 1990 3
Philips Semiconductors Product specification
Triple 3-input OR gate 74HC/HCT4075
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
3, 1, 11 1A to 3A data inputs
4, 2, 12 1B to 3B data inputs
5, 8, 13 1C to 3C data inputs
6, 9, 10 1Y to 3Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUT
nA nB nC nY
L
H
X
X
L
X
H
X
L
X
X
H
L
H
H
H
Page 4
December 1990 4
Philips Semiconductors Product specification
Triple 3-input OR gate 74HC/HCT4075
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC to nY
28
10
8
100
20
17
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.6
Page 5
December 1990 5
Philips Semiconductors Product specification
Triple 3-input OR gate 74HC/HCT4075
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: SSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr= tf= 6 ns; CL= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
INPUT UNIT LOAD COEFFICIENT
nA, nB, nC 1.50
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nA, nB, nC to nY
12 24 30 36 ns 4.5 Fig.6
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.6
Fig.6 Waveforms showing the input (nA, nB, nC) to output (nY) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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