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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT165
8-bit parallel-in/serial-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
FEATURES
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Output capability: standard
• ICC category: MSI
When PL is HIGH, data enters the register serially at the
Dsinput and shifts one place to the right
(Q0→ Q1→ Q2, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q7output to the DSinput of the
succeeding stage.
The clock input is a gated-OR structure which allows one
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
7
and
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
Q7) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D0to
D7inputs are loaded into the register asynchronously.
APPLICATIONS
• Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay
CP to Q7,Q
PL to Q7,Q
D7 to Q7,Q
7
7
7
CL= 15 pF; VCC= 5 V
maximum clock frequency 56 48 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per
notes 1 and 2 35 35 pF
package
TYPICAL
HC HCT
16
15
11
14
17
11
UNIT
ns
ns
ns
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
December 1990 2
.
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
7
9Q
2 CP clock input (LOW-to-HIGH edge-triggered)
8 GND ground (0 V)
10 D
11, 12, 13, 14, 3, 4, 5, 6 D
15
16 V
PL asynchronous parallel load input (active LOW)
Q
7
7
s
to D
0
7
complementary output from the last stage
serial output from the last stage
serial data input
parallel data inputs
CE clock enable input (active LOW)
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODES INPUTS Q
parallel load L
serial shift
PL CE CP D
X
L
H
H
X
L
L
X
X
↑
↑
X
X
l
h
D0-D
S
7
L
H
X
X
hold “do nothing” H H X X X q
REGISTERS OUTPUTS
n
Q
0
L
H
L
H
0
Note
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the
LOW-to-HIGH clock transition
X = don’t care
↑ = LOW-to-HIGH clock transition
Q1-Q
L - L
H - H
q
0-q5
q0-q
q1-q
6
Q
7
L
H
q
6
q
5
6
6
q
7
Q
7
H
L
q
6
q
6
q
7
Fig.5 Logic diagram.
December 1990 4
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR HC
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
/ t
propagation delay
PLH
CE, CP to Q7, Q
propagation delay
PLH
PL to Q7, Q
propagation delay
PLH
D7to Q7, Q
output transition
TLH
7
7
7
time
t
W
clock pulse width
HIGH or LOW
t
W
parallel load pulse
width; LOW
t
rem
removal time
PL to CP, CE
t
su
set-up time
Dsto CP, CE
t
su
set-up time
CE to CP;
CP to CE
t
su
set-up time
Dnto PL
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
52
80
16
14
80
16
14
100
20
17
80
16
14
80
16
14
80
16
14
19
15
50
18
14
36
13
10
19
7
6
17
6
5
14
5
4
22
8
6
11
4
3
17
6
5
22
8
6
165
33
28
165
33
28
120
24
20
75
15
13
100
20
17
100
20
17
125
25
21
100
20
17
100
20
17
100
20
17
205
41
35
205
41
35
150
30
26
95
19
16
250
50
43
250
50
43
180
36
31
110
22
19
120
24
20
120
24
20
150
30
26
120
24
20
120
24
20
120
24
20
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
December 1990 5
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
T
SYMBOL PARAMETER
t
h
hold time
Dsto CP, CE
Dnto PL
t
h
hold time
CE to CP
CP to CE
f
max
maximum clock
pulse frequency
(°C)
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
5
5
5
5
5
5
6
30
35
6
2
2
−17
−6
−5
17
51
61
5
5
5
5
5
5
5
24
28
5
5
5
5
5
5
4
20
24
UNIT
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.6
4.5
6.0
Fig.6
4.5
6.0
Fig.6
4.5
6.0
December 1990 6
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D
D
CP
CE
PL
n
s
0.35
0.35
0.65
0.65
0.65
December 1990 7
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
CE, CP to Q7, Q
t
PHL
/ t
propagation delay
PLH
PL to Q7, Q
t
PHL
/ t
propagation delay
PLH
D7to Q7, Q
t
THL
t
W
/ t
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
clock pulse width
HIGH or LOW
t
W
parallel load pulse
width; LOW
t
rem
removal time
PL to CP, CE
t
su
set-up time
Dsto CP, CE
t
su
set-up time
CE to CP; CP to CE
t
su
set-up time
Dnto PL
t
h
hold time
Dsto CP, CE; Dnto PL
t
h
hold time
CE to CP, CP to CE
f
max
maximum clock pulse
frequency
T
amb
(°C)
TEST CONDITIONS
74HCT
+25 −40 to +85 −40 to +125
UNIT
WAVEFORMS
V
CC
(V)
min. typ. max. min. max. min. max.
17 34 43 51 ns 4.5 Fig.6
7
20 40 50 60 ns 4.5 Fig.6
7
14 28 35 42 ns 4.5 Fig.6
7
16 6 20 24 ns 4.5 Fig.6
20 9 25 30 ns 4.5 Fig.6
20 8 25 30 ns 4.5 Fig.6
20 2 25 30 ns 4.5 Fig.6
20 7 25 30 ns 4.5 Fig.6
20 10 25 30 ns 4.5 Fig.6
7 −1 9 11 ns 4.5 Fig.6
0 −7 0 0 ns 4.5 Fig.6
26 44 21 17 MHz 4.5 Fig.6
December 1990 8
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
AC WAVEFORMS
The changing to output assumes internal Q
opposite state from Q7.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
6
Fig.6 Waveforms showing the clock (CP) to output (Q7or Q7) propagation delays, the clock pulse width, the
output transition times and the maximum clock frequency.
The changing to output assumes internal Q
opposite state from Q7.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
6
Fig.7 Waveforms showing the parallel load (PL) pulse width, the parallel load to output (Q7or Q7) propagation
delays, the parallel load to clock (CP) and clock enable (CE) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the data input (Dn) to output (Q7or Q7) propagation delays when PL is LOW.
December 1990 9
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Philips Semiconductors Product specification
8-bit parallel-in/serial-out shift register 74HC/HCT165
CE may change only from HIGH-to-LOW while CP
is LOW.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
Fig.9 Waveforms showing the set-up and hold times from the serial data input (Ds) to the clock (CP) and clock
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
enable (CE) inputs, from the clock enable input (CE) to the clock input (CP) and from the clock input (CP)
to the clock enable input (CE).
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.10 Waveforms showing the set-up and hold times from the data inputs (Dn) to the parallel load input (PL).
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 10
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