Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
September 1993
INTEGRATED CIRCUITS
74HC/HCT154
4-to-16 line decoder/demultiplexer
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
September 1993 2
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
FEATURES
• 16-line demultiplexing capability
• Decodes 4 binary-coded inputs into one of 16 mutually
exclusive outputs
• 2-input enable gate for strobing or expansion
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT154 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT154 decoders accept four active HIGH
binary address inputs and provide 16 mutually exclusive
active LOW outputs.
The 2-input enable gate can be used to strobe the decoder
to eliminate the normal decoding “glitches” on the outputs,
or it can be used for the expansion of the decoder.
The enable gate has two AND’ed inputs which must be
LOW to enable the outputs.
The “154” can be used as a 1-to-16 demultiplexer by using
one of the enable inputs as the multiplexed data input.
When the other enable is LOW, the addressed output will
follow the state of the applied data.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/ tPLH
propagation delay An, En to Y
n
CL= 15 pF; VCC=5 V 11 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 60 60 pF
Page 3
September 1993 3
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17
Y0 to Y
15
outputs (active LOW)
18, 19
E0, E
1
enable inputs (active LOW)
12 GND ground (0 V)
23, 22, 21, 20 A
0
to A
3
address inputs
24 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
(a) (b)
Fig.4 Functional diagram.
Page 4
September 1993 4
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS
E0E1A0A1A2A3Y0Y1Y2Y3Y4Y5Y6Y7Y8Y9Y10Y11Y12Y13Y14Y
15
H
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
Fig.5 Logic diagram.
Page 5
September 1993 5
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
An to Y
n
36
13
10
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
En to Y
n
39
14
11
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Figs 6 and 7
Page 6
September 1993 6
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
A
n
E
n
1.0
1.0
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
An to Y
n
16 35 44 53 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
En to Y
n
15 32 40 48 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
Page 7
September 1993 7
Philips Semiconductors Product specification
4-to-16 line decoder/demultiplexer 74HC/HCT154
AC WAVEFORMS
Fig.6 Waveforms showing the address input (An) to
output (Yn) propagation delays and the output
transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the enable input (En)
to output (Yn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
APPLICATION INFORMATION
Fig.8 1-of-16 decoder; LOW level output is selected.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 1-of-16 demultiplexer; logic level on selected
outputs follow the logic level on the data input.
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