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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT138
3-to-8 line decoder/demultiplexer;
inverting
Product specification
File under Integrated Circuits, IC06
September 1993
Page 2
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138
FEATURES
• Demultiplexing capability
• Multiple input enable for easy expansion
• Ideal for memory chip select decoding
• Active LOW mutually exclusive outputs
• Output capability: standard
• ICCcategory: MSI
The 74HC/HCT138 decoders accept three binary
weighted address inputs (A
provide 8 mutually exclusive active LOW outputs (Y0to
Y7).
The “138” features three enable inputs: two active LOW
(E1and E2) and one active HIGH (E3). Every output will be
HIGH unless E1and E2are LOW and E3is HIGH.
This multiple enable function allows easy parallel
expansion of the “138” to a 1-of-32 (5 lines to 32 lines)
decoder with just four “138” ICs and one inverter.
GENERAL DESCRIPTION
The 74HC/HCT138 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The ”138” can be used as an eight output demultiplexer by
using one of the active LOW enable inputs as the data
input and the remaining enable inputs as strobes. Unused
enable inputs must be permanently tied to their
appropriate active HIGH or LOW state.
The ”138” is identical to the “238” but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr= tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
= 15 pF; VCC= 5 V
L
t
PHL
t
PHL
C
C
I
PD
propagation delay C
/ t
PLH
/ t
PLH
Anto Y
E3to Y
Ento Y
n
n
n
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 67 67 pF
, A1, A2) and when enabled,
0
TYPICAL
HC HCT
12 17 ns
14 19 ns
UNIT
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD= CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
September 1993 2
.
Page 3
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 2, 3 A
4, 5
6E
8 GND ground (0 V)
15, 14, 13, 12, 11, 10, 9, 7
16 V
to A
0
2
E1, E
2
3
Y0 to Y
7
CC
address inputs
enable inputs (active LOW)
enable input (active HIGH)
outputs (active LOW)
positive supply voltage
handbook, halfpage
1
2
3
4
5
6
A
0
A
1
A
2
E
1
E
2
E
3
Y
Y
Y
Y
Y
Y
Y
Y
MLB312
0
1
2
3
4
5
6
7
Fig.1 Pin configuration. Fig.2 Logic symbol.
15
14
13
12
11
10
9
7
(a) (b)
Fig.3 IEC logic symbol.
September 1993 3
Fig.4 Functional diagram.
Page 4
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138
FUNCTION TABLE
INPUTS OUTPUTS
E
H
X
X
L
L
L
L
L
L
L
L
E
1
X
H
X
L
L
L
L
L
L
L
L
E
2
3
X
X
L
H
H
H
H
H
H
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
A
X
X
X
L
H
L
H
L
H
L
H
A
0
X
X
X
L
L
H
H
L
L
H
H
A
1
X
X
X
L
L
L
L
H
H
H
H
Y
2
H
H
H
L
H
H
H
H
H
H
H
Y
0
H
H
H
H
L
H
H
H
H
H
H
Y
1
H
H
H
H
H
L
H
H
H
H
H
Y
2
H
H
H
H
H
H
L
H
H
H
H
Y
3
H
H
H
H
H
H
H
L
H
H
H
Y
4
H
H
H
H
H
H
H
H
L
H
H
Y
5
H
H
H
H
H
H
H
H
H
L
H
Y
6
7
H
H
H
H
H
H
H
H
H
H
L
Fig.5 Logic diagram.
September 1993 4
Page 5
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
SYMBOL PARAMETER
min. typ. max. min. max. min. max.
t
PHL
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
/ t
propagation delay
PLH
PLH
PLH
TLH
Anto Y
propagation delay
E3to Y
propagation delay
Ento Y
output transition
time
n
n
n
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
41
15
12
47
17
14
47
17
14
19
7
6
150
30
26
150
30
26
150
30
26
75
15
13
190
38
33
190
38
33
190
38
33
95
19
16
225
45
38
225
45
38
225
45
38
110
22
19
.
UNIT
ns
ns
ns
ns
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
2.0
4.5
Fig.6
6.0
2.0
4.5
Fig.6
6.0
2.0
4.5
Fig.7
6.0
2.0
4.5
Figs 6 and 7
6.0
September 1993 5
Page 6
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications. To
CC
determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
A
n
E
n
E
3
1.50
1.25
1.00
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= tf= 6 ns; CL= 50 pF
r
T
amb
(°C)
74HCT
SYMBOL PARAMETER
UNIT
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
/ t
propagation delay
PLH
PLH
PLH
TLH
Anto Y
propagation delay
E3to Y
propagation delay
Ento Y
output transition
time
n
n
n
20 35 44 53 ns 4.5 Fig.6
18 40 50 60 ns 4.5 Fig.6
19 40 50 60 ns 4.5 Fig.7
7 15 19 22 ns 4.5 Figs 6 and 7
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
September 1993 6
Page 7
Philips Semiconductors Product specification
3-to-8 line decoder/demultiplexer; inverting 74HC/HCT138
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the address input (An) and enable input (E3) to output (Yn) propagation delays and
the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the enable input (En) to output (Yn) propagation delays and the output transition
times.
PACKAGE OUTLINES
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
See
.
September 1993 7
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