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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT02
Quad 2-input NOR gate
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC/HCT02 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT02 provide the 2-input NOR function.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
C
C
I
PD
/ t
PLH
propagation delay nA, nB to nY CL= 15 pF; VCC=5V 7 9 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per gate notes 1 and 2 22 24 pF
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi + ∑ (CL× V
CC
2
× fO) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
2. For HC the condition is VI= GND to V
2
× fo) = sum of outputs
CC
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
TYPICAL
UNIT
HC HCT
December 1990 2
Page 3
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 4, 10, 13 1Y to 4Y data outputs
2, 5, 8, 11 1A to 4A data inputs
3, 6, 9, 12 1B to 4B data inputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
FUNCTION TABLE
INPUTS OUTPUT
nA nB nY
L
L
H
H
Notes
1. H = HIGH voltage level
L = LOW voltage level
Fig.4 Functional diagram. Fig.5 Logic diagram (one gate).
L
H
L
H
H
L
L
L
December 1990 3
Page 4
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
t
THL
/ t
/ t
propagation delay
PLH
TLH
nA, nB to nY
output transition time
(°C) TEST CONDITIONS
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
25
9
7
19
7
6
90
18
15
75
15
13
115
23
20
95
19
16
135
27
23
110
22
19
.
UNIT
ns
ns
V
(V)
2.0
4.5
6.0
2.0
4.5
6.0
CC
WAVEFORMS
Fig.6
Fig.6
December 1990 4
Page 5
Philips Semiconductors Product specification
Quad 2-input NOR gate 74HC/HCT02
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: SSI
Notes to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOADCOEFFICIENT
nA, nB 1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; tr=tf= 6 ns; CL= 50 pF
(°C) TEST CONDITIONS
T
amb
74HCT
SYMBOL PARAMETER
+25 −40 to+85 −40 to+125
UNIT
V
(V)
CC
min. typ. max. min. max. min. max.
t
PHL
t
THL
/ t
/ t
propagation delay
PLH
nA, nB to nY
output transition time 7 15 19 22 ns 4.5 Fig.6
TLH
11 19 24 29 ns 4.5 Fig.6
WAVEFORMS
AC WAVEFORMS
HC: VM= 50%; VI= GND to V
HCT: VM= 1.3 V; VI= GND to 3 V.
CC
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays and the output transition times.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 5
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