
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT541
Octal buffer/line driver; 3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state 74HC/HCT541
FEATURES
• Non-inverting outputs
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT541 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT541 are octal non-inverting buffer/line
drivers with 3-state outputs. The 3-state outputs are
controlled by the output enable inputs
OE1and OE2.
A HIGH on OEncauses the outputs to assume a high
impedance OFF-state.
The “541” is identical to the “540” but has non-inverting
outputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay Anto Y
n
CL= 15 pF; VCC= 5 V 10 12 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per buffer notes 1 and 2 37 39 pF

December 1990 3
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state 74HC/HCT541
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 19
OE1, OE
2
output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8, 9 A
0
to A
7
data inputs
10 GND ground (0 V)
18, 17, 16, 15, 14, 13, 12, 11 Y
0
to Y
7
bus outputs
20 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 4
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state 74HC/HCT541
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high impedance OFF-state
INPUTS OUTPUT
OE
1
OE
2
A
n
Y
n
L
L
X
H
L
L
H
X
L
H
X
X
L
H
Z
Z
Fig.5 Logic diagram.

December 1990 5
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state 74HC/HCT541
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Anto Y
n
33
12
10
115
23
20
145
29
25
175
35
30
ns 2.0
4.5
6.0
Fig.6
t
PZH
/ t
PZL
3-state output
enable time
OE to Y
n
55
20
16
160
32
27
200
40
34
240
48
41
ns 2.0
4.5
6.0
Fig.7
t
PHZ
/ t
PLZ
3-state output
disable time
OE to Y
n
61
22
18
160
32
27
200
40
34
240
48
41
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6

December 1990 6
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state 74HC/HCT541
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICCper input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
OE
1
OE
2
A
n
1.50
1.00
0.70
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Anto Y
n
15 28 35 42 ns 4.5 Fig.6
t
PZH
/ t
PZL
3-state output enable time
OE to Y
n
21 35 44 53 ns 4.5 Fig.7
t
PHZ
/ t
PLZ
3-state output disable time
OE to Y
n
21 35 44 53 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time
5 12 15 18 ns 4.5 Fig.6

December 1990 7
Philips Semiconductors Product specification
Octal buffer/line driver; 3-state 74HC/HCT541
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.6 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.