Datasheet 74HC-HCT4514 Datasheet (Philips)

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INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT4514

4-to-16 line decoder/demultiplexer with input latches

Product speciﬁcation File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with input latches

FEATURES

• Non-inverting outputs

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT4514 are high-speed Si-gate CMOS devices and are pin compatible with “4514” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

t

PHL

C C

I PD

/ t

PLH

propagation delay An to Q

n

input capacitance 3.5 3.5 pF power dissipation capacitance per package notes 1 and 2 44 45 pF

The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted address inputs (A (LE), and an active LOW enable input (E). The 16 outputs (Q0to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at Anare stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is HIGH. At E HIGH, all outputs are LOW. The enable input (E) does not affect the state of the latch.

When the “4514” is used as a demultiplexer, E is the data input and A0to A3are the address inputs.

CL= 15 pF; VCC=5 V 23 26 ns

74HC/HCT4514

to A3), with latches, a latch enable input

0

TYPICAL

HC HCT

UNIT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz fo= output frequency in MHz ∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

September 1993 2

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with

74HC/HCT4514

input latches

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1 LE latch enable input (active HIGH) 2, 3, 21, 22 A 11, 9, 10, 8, 7, 6, 5, 4, 18, 17, 20, 19, 14, 13, 16, 15 Q 12 GND ground (0 V) 23 24 V

to A

0

to Q

0

E enable input (active LOW)

CC

address inputs

3

multiplexer outputs (active HIGH)

15

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

September 1993 3

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with input latches

Fig.4 Functional diagram.

FUNCTION TABLE

74HC/HCT4514

APPLICATIONS

• Digital multiplexing

• Address decoding

• Hexadecimal/BCD decoding

INPUTS OUTPUTS

EA0A1A2A3Q0Q1Q2Q3Q4Q5Q6Q7Q8Q9Q10Q11Q12Q13Q14Q

HXXXXLLLLLLLLLLLLLLLL

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

H

L

L L L L

L L

H

L

15

L L L L

L L L

H

Notes

1. LE = HIGH H = HIGH voltage level L = LOW voltage level X = don’t care

September 1993 4

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with input latches

74HC/HCT4514

Fig.5 Logic diagram.

September 1993 5

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with input latches

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see Output capability: standard

ICCcategory: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

THL

t

W

/ t

propagation delay

PLH

An to Q

propagation delay

PLH

propagation delay

PLH

E to Q

output transition time 19

TLH

LE to Q

n

latch enable pulse width

HIGH

t

su

set-up time

Anto LE

t

h

hold time

Anto LE

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

74

230

27

46

22

39

74

230

27

46

22

39

41

175

15

35

12

30 75

7

15

6

13

80

14

16

5

14

4

90

25

18

9

15

7

1

−11

1

−4

1

−3

T

amb

100 20 17

115 23 20

1 1 1

(°C)

74HC

290 58 49

220 44 37

95 19 16

120 24 20

135 27 23

1 1 1

345 69 59

265 53 45

110 22 19

74HC/HCT4514

.

TEST CONDITIONS

UNIT

ns 2.0

V

(V)

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

CC

WAVEFORMS

Fig.6

Fig.7

September 1993 6

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with

74HC/HCT4514

input latches

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see Output capability: standard

ICCcategory: MSI

Note to HCT types

The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆I

per input, multiply this value by the unit load coefficient shown in the table below.

CC

INPUT UNIT LOAD COEFFICIENT

A LE E

n

0.65

1.40

1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PHL

t

THL

/ t

propagation delay

PLH

An to Q

propagation delay

PLH

LE to Q

propagation delay

PLH

E to Q

output transition time

TLH

n

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

(°C)

T

amb

74HCT

+25 −40 to +85 −40 to +125

min. typ. max. min. max. min. max.

30 55 69 83 ns 4.5 Fig.6

29 50 63 75 ns 4.5 Fig.6

17 40 50 60 ns 4.5 Fig.6

7 15 19 22 ns 4.5 Fig.6

.

TEST CONDITIONS

UNIT

WAVEFORMS

V

CC

(V)

t

W

t

su

t

h

latch enable pulse width

HIGH

set-up time

Anto LE

hold time

Anto LE

16 4 20 24 ns 4.5 Fig.7

18 9 23 27 ns 4.5 Fig.7

3 −3 3 3 ns 4.5 Fig.7

September 1993 7

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with

74HC/HCT4514

input latches

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

Fig.6 Waveforms showing the input (An, LE, E) to output (Qn) propagation delays and the output transition times.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

The shaded areas indicate when the input is permitted to change for predictable output performance.

(1) HC : V

HCT: V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

M

Fig.7 Waveforms showing the minimum pulse width of the latch enable input (LE) and the set-up and hold times

for LE to An. Set-up and hold times are shown as positive values but may be specified as negative values.

September 1993 8

Philips Semiconductors Product speciﬁcation

4-to-16 line decoder/demultiplexer with input latches

APPLICATION INFORMATION

74HC/HCT4514

Fig.8 Code-to-code conversion; hexadecimal to BCD.

PACKAGE OUTLINES

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

See

September 1993 9

.