Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC58
Dual AND-OR gate
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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December 1990 2
Philips Semiconductors Product specification
Dual AND-OR gate 74HC58
FEATURES
• Output capability: standard
• ICC category: SSI
GENERAL DESCRIPTION
The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard no. 7A.
The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and
the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 15 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
CL= output load capacitance in pF
VCC= supply voltage in V
∑ (CL× V
CC
2
× fo) = sum of outputs
2. For HC the condition is VI= GND to V
CC
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
1n to 1Y 11 ns
2n to 2Y 9 ns
C
I
input capacitance 3.5 pF
C
PD
power dissipation capacitance per
gate
notes 1 and 2 18 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
Dual AND-OR gate 74HC58
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 12, 13, 9, 10, 11 1A to 1F data inputs
2, 3, 4, 5 2A to 2D data inputs
8, 6 1Y, 2Y data outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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December 1990 4
Philips Semiconductors Product specification
Dual AND-OR gate 74HC58
Fig.4 Functional diagram. Fig.5 Logic diagram.
FUNCTION TABLE
(1)
INPUTS OUTPUT
1A 1B 1C 1D 1E 1F 1Y
L
L
L
X
X
X
X
X
L
L
X
X
X
X
X
L
X
X
L
X
X
L
X
X
L
X
X
L
X
X
L
L
L
L
L
X
X
X
X
X
H
L
X
X
X
X
H
X
L
L
L
X
H
X
L
X
X
H
X
X
X
L
X
H
X
L
X
X
L
H
X
L
L
L
L
H
H
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUT
2A 2B 2C 2D 2Y
L
L
X
X
X
H
X
X
L
L
X
H
L
X
L
X
H
X
X
L
X
L
H
X
L
L
L
L
H
H
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December 1990 5
Philips Semiconductors Product specification
Dual AND-OR gate 74HC58
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: SSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
1A,1B,1C,1D,1E,
1F to 1Y
36
13
10
115
23
20
145
29
25
175
35
30
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
2A,2B,2C,2D to 2Y
30
11
9
100
20
17
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.6
t
THL
/ t
TLH
output transition
time
19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.6
Fig.6 Waveforms showing the input (nA, nB, nC, nD, 1E, 1F) to output (nY) propagation delays and the output
transition times.
(1) HC : VM= 50%; VI= GND to VCC.
handbook, full pagewidth
MBA336
t
PHL
V
M
(1)
t
THL
t
PLH
t
TLH
V
M
(1)
nA, nB, nC, nD,
1E, 1F INPUT
nY OUTPUT
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