Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT564
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge
trigger; 3-state; inverting
74HC/HCT564
FEATURES
• 3-state inverting outputs for bus oriented applications
• 8-bit positive-edge triggered register
• Common 3-state output enable input
• Independent register and 3-state buffer operation
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT564 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT564 are octal D-type flip-flops featuring
separate D-type inputs for each flip-flop and inverting
3-state outputs for bus oriented applications. A clock (CP)
and an output enable
(OE) input are common to all
flip-flops.
The 8 flip-flops will store the state of their individual
D-inputs that meet the set-up and hold times requirements
on the LOW-to-HIGH CP transition.
When OE is LOW, the contents of the 8 flip-flops are
available at the outputs.
When OE is HIGH, the outputs go to the high impedance
OFF-state. Operation of the OE input does not affect the
state of the flip-flops.
The “564” is functionally identical to the “574” but has
inverting outputs. The “564” is functionally identical to the
“534”, but has a different pinning.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/ tPLH
propagation delay CP to Q
n
CL= 15 pF; VCC=5 V 15 16 ns
f
max
maximum clock frequency 127 62 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2 27 27 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1
OE 3-state output enable input (active LOW)
2, 3, 4, 5, 6, 7, 8, 9 D
0
to D
7
data inputs
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH, edge-triggered)
19, 18, 17, 16, 15, 14, 13, 12
Q0 to Q
7
3-state flip-flop outputs
20 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH
CP transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the LOW-to-HIGH
CP transition
Z = high impedance OFF-state
↑ = LOW-to-HIGH clock transition
OPERATING
MODES
INPUTS
INTERNAL
FLIP-FLOPS
OUTPUTS
OE CP D
n
Q0to Q
7
load and read
register
L
L
↑
↑
l
h
L
H
H
L
load register and
disable outputs
H
H
↑
↑
l
h
L
H
Z
Z
Fig.5 Logic diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
50
18
14
165
33
28
205
41
35
250
50
43
ns 2.0
4.5
6.0
Fig.6
t
PZH
/ t
PZL
3-state output enable
time
OE to Q
n
44
16
13
140
28
24
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.8
t
PHZ
/ t
PLZ
3-state output disable
time
OE to Q
n
50
18
14
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6
t
W
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.6
t
su
set-up time
Dn to CP
60
12
10
6
2
2
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.7
t
h
hold time
Dn to CP
5
5
5
0
0
0
5
5
5
5
5
5
ns 2.0
4.5
6.0
Fig.7
f
max
maximum clock pulse
frequency
6.0
30
35
38
115
137
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.6
Page 6
December 1990 6
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
OE
D0 to D
7
CP
0.80
0.25
1.00
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
n
19 35 44 53 ns 4.5 Fig.6
t
PZH
/ t
PZL
3-state output enable
time OE to Q
n
19 35 44 53 ns 4.5 Fig.8
t
PHZ
/ t
PLZ
3-state output disable
time OE to Q
n
19 30 38 45 ns 4.5 Fig.8
t
THL
/ t
TLH
output transition time 5 12 15 18 ns 4.5 Fig.6
t
W
clock pulse width
HIGH or LOW
18 8 23 27 ns 4.5 Fig.6
t
su
set-up time
Dn to CP
12 3 15 18 ns 4.5 Fig.7
t
h
hold time
Dn to CP
3 −2 3 3 ns 4.5 Fig.7
f
max
maximum clock pulse
frequency
27 56 22 18 MHz 4.5 Fig.6
Page 7
December 1990 7
Philips Semiconductors Product specification
Octal D-type flip-flop; positive-edge trigger;
3-state; inverting
74HC/HCT564
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to
output (Qn) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the data set-up and
hold times for the data input (Dn).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and
disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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