Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4511
BCD to 7-segment
latch/decoder/driver
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
FEATURES
• Latch storage of BCD inputs
• Blanking input
• Lamp test input
• Driving common cathode LED displays
• Guaranteed 10 mA drive capability per output
• Output capability: non-standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4511 are high-speed Si-gate CMOS
devices and are pin compatible with “4511” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4511 are BCD to 7-segment
latch/decoder/drivers with four address inputs (D
1
to D4),
an active LOW latch enable input (LE), an active LOW
ripple blanking input (BI), an active LOW lamp test input
(LT), and seven active HIGH segment outputs (Qa to Qg).
When LE is LOW, the state of the segment outputs (Qa to
Qg) is determined by the data on D1 to D4.
When LE goes HIGH, the last data present on D1 to D4 are
stored in the latches and the segment outputs remain
stable.
When LT is LOW, all the segment outputs are HIGH
independent of all other input conditions. With LT HIGH, a
LOW onBI forces all segment outputs LOW. The inputsLT
and BI do not affect the latch circuit.
APPLICATIONS
• Driving LED displays
• Driving incandescent displays
• Driving fluorescent displays
• Driving LCD displays
• Driving gas discharge displays
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC=5 V
D
n
to Q
n
24 24 ns
LE to Q
n
23 24 ns
BI to Q
n
19 20 ns
LT to Q
n
12 13 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per latch notes 1 and 2 64 64 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
3
LT lamp test input (active LOW)
4
BI ripple blanking input (active LOW)
5
LE latch enable input (active LOW)
7, 1, 2, 6 D
1
to D
4
BCD address inputs
8 GND ground (0 V)
13, 12, 11, 10, 9, 15, 14 Q
a
to Q
g
segments outputs
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
FUNCTION TABLE
Note
1. Depends upon the BCD-code applied during the LOW-to-HIGH transition of
LE.
H = HIGH voltage level
L = LOW voltage level
X = don’t care
INPUTS OUTPUTS
DISPLAY
LE BI LTD4D3D2D1QaQbQcQdQeQfQ
g
XXLXXXX HHHHHH H8
XLHXXXX LLLLLLLblank
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
H
L
H
H
H
H
H
H
H
H
L
H
H
L
H
H
H
L
H
L
H
L
L
L
L
L
H
H
0
1
2
3
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
L
H
L
H
H
L
L
H
H
H
H
H
L
H
H
L
L
L
H
L
H
H
H
L
H
H
H
L
4
5
6
7
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
H
H
L
L
H
H
L
L
H
H
L
L
H
L
L
L
H
L
L
L
H
H
L
L
H
H
L
L
8
9
blank
blank
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
blank
blank
blank
blank
HHHXXXX
(1) (1)
Fig.4 Functional diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
Fig.5 Logic diagram.
Fig.6 Segment designation.
Fig.7 Display.
Page 6
December 1990 6
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard, excepting VOH which is given below
ICC category: MSI
Non-standard DC characteristics for 74HC
Voltages are referenced to GND (ground = 0 V)
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST
CONDITIONS
74HC
V
CC
(V)
V
I
−I
O
(mA)
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
V
OH
HIGH level output voltage 3.98
3.60
3.84
3.35
3.70
3.10
V 4.5 VIH or
V
IL
7.5
10.0
V
OH
HIGH level output voltage 5.60
5.48
4.80
5.45
5.34
4.50
5.35
5.20
4.20
V 6.0 VIH or
V
IL
7.5
10.0
15.0
Page 7
December 1990 7
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Dn to Q
n
77
28
22
300
60
51
375
75
64
450
90
77
ns 2.0
4.5
6.0
Fig.8
t
PHL
/ t
PLH
propagation delay
LE to Q
n
74
27
22
270
54
46
330
68
58
405
81
69
ns 2.0
4.5
6.0
Fig.9
t
PHL
/ t
PLH
propagation delay
BI to Q
n
61
22
18
220
44
37
275
55
47
330
66
56
ns 2.0
4.5
6.0
Fig.10
t
PHL
/ t
PLH
propagation delay
LT to Q
n
41
15
12
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Figs 8, 9 and
10
t
W
latch enable pulse width
LOW
80
16
14
11
4
3
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.9
t
su
set-up time
Dn to LE
60
12
10
14
5
4
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.11
t
h
hold time
Dn to LE
0
0
0
−11
−4
−3
0
0
0
0
0
0
ns 2.0
4.5
6.0
Fig.11
Page 8
December 1990 8
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard, excepting VOHwhich is given below
ICC category: MSI
Non-standard DC characteristics for 74HCT
Voltages are referenced to GND (ground = 0 V)
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST
CONDITIONS
74HCT
V
CC
(V)
V
I
−I
O
(mA)
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
V
OH
HIGH level output voltage 3.98
3.60
3.84
3.35
3.70
3.10
V 4.5 VIH or
V
IL
7.5
10.0
INPUT UNIT LOAD COEFFICIENT
LT, LE
BI, D
n
1.50
0.30
Page 9
December 1990 9
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Dn to Q
n
28 60 75 90 ns 4.5 Fig.8
t
PHL
/ t
PLH
propagation delay
LE to Q
n
27 54 68 81 ns 4.5 Fig.9
t
PHL
/ t
PLH
propagation delay
BI to Q
n
23 44 55 66 ns 4.5 Fig.10
t
PHL
/ t
PLH
propagation delay
LT to Q
n
16 30 38 45 ns 4.5 Fig.8
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Figs 8, 9 and
10
t
W
latch enable pulse
width
LOW
16 5 20 24 ns 4.5 Fig.9
t
su
set-up time
Dn to LE
12 5 15 18 ns 4.5 Fig.11
t
h
hold time
Dn to LE
0 −4 0 0 ns 4.5 Fig.11
Page 10
December 1990 10
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
AC WAVEFORMS
Fig.8 Waveforms showing the input (Dn, LT) to
output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.9 Waveforms showing the input (LE) to output
(Qn) propagation delays and the latch
enable pulse width.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the input (BI) to output
(Qn) propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.11 Waveforms showing the data set-up and
hold times for Dn input to LE input.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Page 11
December 1990 11
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
APPLICATION DIAGRAMS
Fig.12 Connection to common cathode LED
display readout.
Fig.13 Connection to common anode LED display
readout.
Fig.14 Connection to incandescent display readout.
(1) A filament pre-warm resistor to reduce
thermal shock and to increase effective cold
resistance of the filament is recommended.
Fig.15 Connection to fluorescent display readout.
Fig.16 Connection to gas discharge display readout.
Fig.17 Connection to LCD display readout.
(Direct DC drive is not recommended as it
can shorten the life of LCD displays).
Page 12
December 1990 12
Philips Semiconductors Product specification
BCD to 7-segment latch/decoder/driver 74HC/HCT4511
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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