Datasheet 74hc4352, 74hc4351 Datasheet

Data sheet acquired from Harris Semiconductor

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SCHS213A

September 1998 - Revised May 2000

CD54/74HC4351, CD74HCT4351,

CD74HC4352

High Speed CMOS Logic

Analog Multiplexers/Demultiplexers with Latch

[ /Title
(CD74
HC435
1,
CD74
HCT43
51,
CD74
HC435

2)
Sub­ect

(High
Speed
CMOS
Logic
Ana­log
Multi­plex­ers/De
multi­plex­ers
with
Latch)

Autho

r ()

Key-

words
(High
Speed
CMOS
Logic

Features

• Wide Analog Input Voltage Range . . . . . . . . . ±5V (Max)

• Low “On” Resistance

-V

- VEE = 4.5V. . . . . . . . . . . . . . . . . . . . . .70Ω (Typ)

CC

- VEE = 9V . . . . . . . . . . . . . . . . . . . . . . .40Ω (Typ)

-V

CC

• Low Crosstalk Between Switches

• Fast Switching and Propagation Speeds

• “Break-Before-Make” Switching

o

• Wide Operating Temperature Range . . . -55

C to 125oC

• HC Types

- 2V to 6V Operation, Control; 0V to 10V Switch

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

CC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation, Control; 0V to 10V Switch

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

OH

Description

The ’HC4351, CD74HCT4351, and CD74HC4352 are
digitally controlled analog switches which utilize silicon-gate
CMOS technology to achieve operating speeds similar to

Pinouts

CD54HC4351

(CERDIP)

CD74HC4351, CD74HCT4351

(PDIP, SOIC)

TOP VIEW

A4
A6

NC

A COMMON

A7
A5
E1
E2

V

EE

GND

1
2
3
4
5
6
7
8
9

10

V

20

CC

A2

19

A1

18

A0

17

A3

16

S0

15

NC

14

S1

13
12

S2

11

LE

LSTTL with the low power consumption of standard CMOS
integrated circuits.

These analog multiplexers/demultiplexers are, in essence,
the HC/HCT4015 and HC4052 preceded by address latches
that are controlled by an active low Latch Enable input (
Two Enable inputs, one active low (

E1), and the other active

LE).

high (E2) are provided allowing enabling with either input
voltage level.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC4351F3A -55 to 125 20 Ld CERDIP
CD74HC4351E -55 to 125 20 Ld PDIP
CD74HC4351M -55 to 125 20 Ld SOIC
CD74HCT4351E -55 to 125 20 Ld PDIP
CD74HC4352E -55 to 125 20 Ld PDIP

NOTES:

1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office
or customer service for ordering information.

1

B0
B2

2

NC

3

B COMMON

B3
B1
E1
E2

V

EE

GND

4
5
6
7
8
9

10

(oC) PACKAGE

CD74HC4352

(PDIP)

TOP VIEW

V

20

CC

A2

19

A1

18

A COMMON

17

A0

16

A3

15

NC

14

S0

13
12

S1

11

LE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2000, Texas Instruments Incorporated

1

Functional Diagram

CD54/74HC4351, CD74HCT4351, CD74HC4352

’HC4351, CD74HCT4351

S0

S1

S2

V

CC

20

15

13

12

11LE

7E1

8E2

LATCHES

LOGIC
LEVEL

CONVERSION

BINARY

TO

1 OF 8

DECODER

WITH

ENABLE

A

CHANNEL IN/OUT

7A6A5A4A3A2A1A0

171819161625

TG

TG

TG

TG

TG

TG

TG

TG

4

A
COMMON
OUT/IN

10 9

GND V

EE

TRUTH TABLE

’HC4351, CD74HCT4351

INPUT STATES (NOTE 3)

“ON”

SWITCHES

LE = HE1 E2 S2 S1 S0

LHLLL A
LHLLH A
LHLHL A
LHLHH A
LHHLL A
LHHLH A
LHHHL A
LHHHH A

H L X X X None

NOTE:

3. When LE is low S0-S2 data are latched and switches cannot
change state.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

An

IN/OUT

FROM
SELECT
LOGIC

0

1

2

3

4

5

6

7

P

V

CC

N

N

V

EE

P
V

CC

A COMMON

IN/OUT

N

N

FIGURE 1. DETAIL OF ONE HC/HCT4351 SWITCH

2

Functional Diagram

13

S0

LATCHES

12

S1

11LE

CD54/74HC4351, CD74HCT4351, CD74HC4352

CD74HC4352

A CHANNELS IN/OUT

S0

S0

S1

S1

CONVERSION

LOGIC
LEVEL

V

CC

20

BINARY

TO

1 OF 4

DECODER

WITH

ENABLE

A3A2A1A

0

16181915

TG

TG

TG

TG

TG

TG

17

4

A COMMON
OUT/IN

B COMMON
OUT/IN

7E1

8E2

10 9

GND V

EE

TRUTH TABLE

CD74HC4352

INPUT STATES (NOTE 4)

“ON”

SWITCHES

LE = HE1 E2 S1 S0

LHLLA
LHLHA
LHHLA
LHHHA

, B

0

0

, B

1

1

, B

2

2

, B

3

3

H L X X None

NOTE:

4. When Latch Enable is “Low” channel-select data is latched and
switches cannot change state.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

TG

TG

1625

B

FROM
SELECT
LOGIC

B

0

B CHANNELS IN/OUT

B

1

3B2

V

CC

N

FIGURE 2. DETAIL OF ONE CD74HC4352 SWITCH

An (Bn)

IN/OUT

P

N

V

EE

P
V

CC

A COMMON (B COMMON)

IN/OUT

N

N

3

CD54/74HC4351, CD74HCT4351, CD74HC4352

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Supply Voltage, V

CC - VEE

. . . . . . . . . . . . . . . . . . -0.5V to 10.5V

DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC 0.5V. . . . . . . . . . . . . . . . . . . . . . . .±20mA

DC Switch Diode Current, I

OK

For VI < VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±25mA

DC Switch Current, IOK (Note 5)

For VI > VEE -0.5V or VI < VCC + 0.5V . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

Supply Voltage Range, V

HC, HCT Types (Figure 3) . . . . . . . . . . . . . . . . . . . . . . .2V to 10V

Supply Voltage Range, V

HC, HCT Types (Figure 4) . . . . . . . . . . . . . . . . . . . . . . . 0V to -6V

DC Input or Output Voltage, VI. . . . . . . . . . . . . . . . . . . GND to V

Analog Switch I/O Voltage, VIS. . . . . . . . . . . . . . . . . . . . . VEE (Min)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VCC (Max)

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

5. In certain applications, the external load-resistor current may include both VCCandsignal-linecomponents.ToavoiddrawingVCCcurrent
when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed 0.6V (cal­culated from RONvalues shown in the DC Electrical Specifications table). No VCCcurrent will flow through RLif the switch current flows
into terminal 3 on the ’HC4351 and CD74HCT4351; terminals 3 and 13 on the CD74HC4352.

6. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

CC -VEE

EE

f

Thermal Resistance (Typical, Note 6) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

Recommended Operating Area as a Function of Supply Voltage

8
6

- GND

V

CC

(V)

HC

4
2
0

024681012

V

CC

- VEE (V)

FIGURE 3. FIGURE 4.

HCT

4

V

CC

- GND
(V)

8
6
4
2
0

0-2-4-6-8

- GND (V)

V

EE

HCT

HC

CD54/74HC4351, CD74HCT4351, CD74HC4352

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

“ON” Resistance
IO = 1mA
Figure 9

Maximum “ON”
Resistance Between
Any Two Channels

Switch On/Off
Leakage Current
4 Channels (4352)

Switch On/Off
Leakage Current
8 Channels (4351)

Control Input Leakage
Current

Quiescent Device
Current
IO = 0

R

∆R

V

V

I

ON

I

IZ

I

IL

CC

IH

IL

ON

TEST CONDITIONS 25oC

V

(V)

EE

V

CC

(V) MIN TYP MAX MIN MAX MIN MAX

-40oC TO
85oC

-55oC TO
125oC

- - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

VCCor V

V

IL

0 4.5 - 70 160 - 200 - 240 Ω

EE

0 6 - 60 140 - 175 - 210 Ω

-4.5 4.5 - 40 120 - 150 - 180 Ω

VCC to V

0 4.5 - 90 180 - 225 - 270 Ω

EE

0 6 - 80 160 - 200 - 240 Ω

-4.5 4.5 - 45 130 - 162 - 195 Ω

- - 04.5-10-----Ω
0 6 -8.5-----Ω

-4.5 4.5 - 5 -----Ω

VIH or

V

IL

For Switch

OFF:

When

VIS = V

CC

VOS=VEE;

When

VIS = VEE,

VOS = V

CC

06--±0.1 - ±1-±1 µA

-5 5 - - ±0.2 - ±2-±2 µA

06--±0.2 - ±2-±2 µA

-5 5 - - ±0.4 - ±4-±4 µA

For Switch

ON:

All

Applicable

Combina-

tions of V

and V

IS

OS

Voltage

Levels

VCCor

-06--±0.1 - ±1-±1 µA

GND

VCCor

GND

When

VIS = VEE,

VOS=VCC,

0 6 - - 8 - 80 - 160 µA

-5 5 - - 16 - 160 - 320 µA

When
VIS = VCC,
VOS = V

EE

UNITSVI(V) VIS(V)

5

CD54/74HC4351, CD74HCT4351, CD74HC4352

DC Electrical Specifications (Continued)

TEST CONDITIONS 25oC

PARAMETER SYMBOL

V

(V)

EE

V

CC

(V) MIN TYP MAX MIN MAX MIN MAX

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

“ON” Resistance
IO = 1mA
Figure 9

V

IH

- - - 4.5 to

2--2-2-V

5.5

V

IL

- - - 4.5 to

- - 0.8 - 0.8 - 0.8 V

5.5

R

ON

VIH or

V

IL

VCCor V

VCC to V

0 4.5 - 70 160 - 200 - 240 Ω

EE

-4.5 4.5 - 40 120 - 150 - 180 Ω
0 4.5 - 90 180 - 225 - 270 Ω

EE

-4.5 4.5 - 45 130 - 162 - 195 Ω

Maximum “ON”
Resistance Between
Any Two Channels

Switch On/Off
Leakage Current
4 Channels (4352)

Switch On/Off
Leakage Current
8 Channels (4351)

∆R

ON

- - 04.5-10-----Ω

-4.5 4.5 - 5 -----Ω

I

VIH or

IZ

V

IL

For Switch

OFF:

When

VIS = V

CC

VOS=VEE;

When

VIS = VEE,

VOS = V

CC

06--±0.1 - ±1-±1 µA

-5 5 - - ±0.2 - ±2-±2 µA

06--±0.2 - ±2-±2 µA

-5 5 - - ±0.4 - ±4-±4 µA

For Switch

ON:

All

Applicable

Combina-

tions of V

and V

IS

OS

Voltage

Levels

Control Input Leakage
Current

Quiescent Device
Current
IO = 0

I

I

CC

VCCor

I

- 0 5.5 - - ±0.1 - ±1-±1 µA

GND

Any

Voltage

Be-

tween

V

CC

and

When

VIS = VEE,

VOS=VCC,

When
VIS = VCC,
VOS = V

EE

0 5.5 - - 8 - 80 - 160 µA

-4.5 5.5 - - 16 - 160 - 320 µA

GND

Additional Quiescent
Device Current Per

∆I

CC

V

-2.1

CC

- - 4.5 to

5.5

- 100 360 - 450 - 490 µA

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) VIS(V)

HCT Input Loading Table

TYPE INPUT UNIT LOADS

All E1, E2, Sn 0.5

(4351, 4352) LE 1.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

6

CD54/74HC4351, CD74HCT4351, CD74HC4352

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Switch In to Switch Out

Maximum Switch Turn “ON”
Delay 4351
E1, E2, LE to V

OS

Maximum Switch Turn “ON”
Delay 4352
E1, E2, LE to V

OS

t

PLH

t

PZH

t

PZH

, tf = 6ns

r

, t

PHL

, t

PZL

, t

PZL

TEST

CONDITIONS

V

(V)

EE

V

(V)

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CL= 50pF 0 2 - - 35 - 45 - 55 ns

0 4.5 - - 7 - 9 - 11 ns
06--6-8-9ns

-4.5 4.5 - - 5 - 7 - 8 ns

CL= 50pF 0 2 - - 300 - 375 - 450 ns

0 4.5 - - 60 - 75 - 90 ns
0 6 - - 51 - 64 - 77 ns

-4.5 4.5 - - 55 - 69 - 83 ns
CL= 15pF - 5 - 27 -----ns
CL= 50pF 0 2 - - 350 - 440 - 525 ns

0 4.5 - - 70 - 88 - 105 ns
0 6 - - 60 - 75 - 90 ns

Maximum Switch Turn “ON”
Delay 4351
Sn to V

OS

Maximum Switch Turn “ON”
Delay 4352
Sn to V

OS

Maximum Switch Turn “OFF”
Delay 4351
E1 to V

OS

t

PZH

t

PZH

t

PHZ

-4.5 4.5 - - 60 - 75 - 90 ns
CL= 15pF - 5 - 35 -----ns

, t

CL= 50pF 0 2 - - 300 - 375 - 450 ns

PZL

0 4.5 - - 60 - 75 - 90 ns
0 6 - - 51 - 64 - 77 ns

-4.5 4.5 - - 50 - 63 - 75 ns
CL= 15pF - 5 - 27 -----ns

, t

CL= 50pF 0 2 - - 375 - 470 - 565 ns

PZL

0 4.5 - - 75 - 94 - 113 ns
0 6 - - 64 - 80 - 96 ns

-4.5 4.5 - - 55 - 69 - 83 ns
CL= 15pF - 5 - 35 -----ns

, t

CL= 50pF 0 2 - - 250 - 315 - 375 ns

PLZ

0 4.5 - - 50 - 63 - 75 ns
0 6 - - 43 - 54 - 64 ns

-4.5 4.5 - - 40 - 50 - 60 ns
CL= 15pF - 5 - 21 -----ns

7

CD54/74HC4351, CD74HCT4351, CD74HC4352

Switching Specifications Input t

PARAMETER SYMBOL

Maximum Switch Turn “OFF”
Delay 4351
E2 to V

OS

Maximum Switch Turn “OFF”
Delay 4351
LE to V

OS

Maximum Switch Turn “OFF”
Delay 4351
Sn to V

OS

t

PHZ

t

PHZ

t

PHZ

, tf = 6ns (Continued)

r

TEST

CONDITIONS

, t

CL= 50pF 0 2 - - 250 - 315 - 375 ns

PLZ

CL= 15pF - 5 - 21 -----ns

, t

, t

CL= 50pF 0 2 - - 275 - 345 - 415 ns

PLZ

CL= 50pF 0 2 - - 275 - 345 - 415 ns

PLZ

V

(V)

EE

V

(V)

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

0 4.5 - - 50 - 63 - 75 ns
0 6 - - 43 - 54 - 64 ns

-4.5 4.5 - - 40 - 50 - 60 ns

0 4.5 - - 55 - 69 - 83 ns
0 6 - - 47 - 59 - 71 ns

-4.5 4.5 - - 45 - 56 - 68 ns

0 4.5 - - 55 - 69 - 83 ns
0 6 - - 47 - 59 - 71 ns

-4.5 4.5 - - 48 - 60 - 71 ns

Maximum Switch Turn “OFF”
Delay 4352
E1, E2, LE to V

OS

Setup Time 4351
Sn to LE

Hold Time 4351 and 4352
Sn to LE

Pulse Width 4351 and 4352
LE

t

PHZ

CL= 15pF - 5 - 21 -----ns

, t

CL= 50pF 0 2 - - 275 - 345 - 415 ns

PLZ

0 4.5 - - 55 - 69 - 83 ns
0 6 - - 47 - 59 - 71 ns

-4.5 4.5 - - 50 - 63 - 75 ns

CL= 15pF - 5 - 21 -----ns

t

SU

CL= 50pF 0 2 - - 60 - 75 - 90 ns

0 4.5 - - 12 - 15 - 18 ns
0 6 - - 10 - 13 - 15 ns

-4.5 4.5 - - 18 - 23 - 27 ns

t

H

CL= 50pF 0 2 5 - - 5 - 5 - ns

04.55--5-5- ns
065--5-5-ns

-4.5 4.5 5 - - 5 - 5 - ns

t

W

CL= 50pF 0 2 100 - - 125 - 150 - ns

0 4.5 20 - - 25 - 30 - ns
0 6 17 - - 21 - 26 - ns

Input (Control) Capacitance C
Power Dissipation Capacitance

C

(Notes 7, 8) 4351

PD

-4.5 4.5 25 - - 31 - 38 - ns

I

- ----10-10-10pF

- -5-50-----pF

8

CD54/74HC4351, CD74HCT4351, CD74HC4352

Switching Specifications Input t

PARAMETER SYMBOL

Power Dissipation Capacitance
(Notes 7, 8) 4352

HCT TYPES

Propagation Delay,
Switch In to Switch Out

Maximum Switch Turn “ON”
Delay 4351
E1, E2, LE to V

OS

Maximum Switch Turn “ON”
Delay 4351
Sn to V

OS

Maximum Switch Turn “OFF”
Delay 4351
E1 to V

OS

t

PLH

t

PZH

t

PZH

t

PHZ

, tf = 6ns (Continued)

r

TEST

CONDITIONS

C

PD

, t

PHL

, t

PZL

- -5-74-----pF

CL= 50pF 0 4.5 - - 7 - 9 - 11 ns

CL= 50pF 0 4.5 - - 75 - 94 - 113 ns

CL= 15pF - 5 - 35 -----ns

, t

CL= 50pF 0 4.5 - - 75 - 94 - 113 ns

PZL

CL= 15pF - 5 - 35 -----ns

, t

CL= 50pF 0 4.5 - - 55 - 69 - 83 ns

PLZ

CL= 15pF - 5 - 23 -----ns

V

(V)

EE

V

(V)

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

-4.5 4.5 - - 5 - 7 - 8 ns

-4.5 4.5 - - 60 - 75 - 90 ns

-4.5 4.5 - - 60 - 75 - 90 ns

-4.5 4.5 - - 40 - 50 - 60 ns

Maximum Switch Turn “OFF”

t

PHZ

Delay 4351
E2 to V

OS

Maximum Switch Turn “OFF”

t

PHZ

Delay 4351
LE to V

OS

Maximum Switch Turn “OFF”

t

PHZ

Delay 4351
Sn to V

OS

Setup Time 4351
Sn to LE

Hold Time 4351 and 4352
Sn to LE

Pulse Width 4351
LE

Input (Control) Capacitance C
Power Dissipation Capacitance

C

(Notes 7, 8) 4351

, t

CL= 50pF 0 4.5 - - 60 - 75 - 90 ns

PLZ

-4.5 4.5 - - 50 - 63 - 75 ns

CL= 15pF - 5 - 23 -----ns

, t

CL= 50pF 0 4.5 - - 60 - 75 - 90 ns

PLZ

-4.5 4.5 - - 55 - 69 - 83 ns

, t

CL= 50pF 0 4.5 - - 65 - 81 - 98 ns

PLZ

-4.5 4.5 - - 55 - 69 - 83 ns
CL= 15pF - 5 - 23 -----ns
CL= 50pF 0 4.5 - - 12 - 15 - 18 ns

-4.5 4.5 - - 14 - 18 - 21 ns
CL= 50pF 0 4.5 5 - - 5 - 5 - ns

-4.5 4.5 5 - - 5 - 5 - ns

t

W

CL= 50pF 0 4.5 25 - - 31 - 28 - ns

-4.5 4.5 25 - - 31 - 38 - ns

I

PD

- ----10-10-10pF

- -5-52-----pF

NOTES:

7. CPD is used to determine the dynamic power consumption, per package.

8. PD=CPDV

2

fi+ Σ (CL+CS)V

CC

2

fowhere fi= input frequency, fo= output frequency, CL= output load capacitance, CS= switch

CC

capacitance, VCC = supply voltage.

9

CD54/74HC4351, CD74HCT4351, CD74HC4352

Analog Channel Specifications T

PARAMETER SYMBOL

Switch Input Capacitance C
Common Capacitance C

Minimum Switch Frequency
Response at -3dB
(Figure 5, 7)

Crosstalk Between Any Two Switches
(Note 12)

Sine-Wave Distortion See Figure 12 All -2.25 2.25 0.035 %

E or S to Switch Feedthrough Noise See Figure 13

Switch “OFF” Signal Feedthrough
(Figure 6, 8)

NOTES:

9. Adjust input voltage to obtain 0dBm at VOS for, fin = 1MHz.

10. VIS is centered at (VCC - VEE)/2.

11. Adjust input for 0dBm.

12. Not applicable for ’HC4351 and CD74HCT4351.

= 25oC

A

I

COM

f

MAX

TEST

CONDITIONS TYPE VEE (V) VCC (V) HC/HCT UNITS

All - - 5 pF
4351 - - 25 pF
4352 - - 12 pF

See Figure 11
Notes 9, 10

See Figure 10
Notes 10, 11

Notes 10, 11

See Figure 14
Notes 10, 11

4351 - - 145 MHz
4352 -2.25 2.25 165 MHz
4351 - - 180 MHz
4352 -4.5 4.5 185 MHz
4351 - - N/A dB
4352 -2.25 2.25 (TBE) dB
4351 - - N/A dB
4352 -4.5 4.5 (TBE) dB

All -4.5 4.5 0.018 %
4351 - - - mV
4352 -2.25 2.25 (TBE) mV
4351 - - - mV
4352 -4.5 4.5 (TBE) mV
4351 - - -73 dB
4352 -2.25 2.25 -65 dB
4351 - - -75 dB
4352 -4.5 4.5 -67 dB

10

CD54/74HC4351, CD74HCT4351, CD74HC4352

Typical Performance Curves

0

VCC = 4.5V

-2

-4

dB

-6

-8

-10
10K 100K 1M 10M 100M

FREQUENCY, f (Hz)

GND = -4.5V

= -4.5V

V

EE

R

= 50Ω

L

PIN 12 TO 3

VCC = 2.25V
GND = -2.25V

= -2.25V

V

EE

R

= 50Ω

L

PIN 12 TO 3

FIGURE 5. CHANNEL ON BANDWIDTH (’HC4351,

CD74HCT4351)

0

VCC = 4.5V

-2

-4

dB

-6

-8

GND = -4.5V

= -4.5V

V

EE

= 50Ω

R

L

PIN 4 TO 3

VCC = 2.25V
GND = -2.25V
V

EE

= 50Ω

R

L

PIN 4 TO 3

= -2.25V

0

-20

-40

dB

-60

-80

-100
10K 100K 1M 10M 100M

FREQUENCY, f (Hz)

VCC = 2.25V
GND = -2.25V
VEE = -2.25V
R

= 50Ω

L

PIN 12 TO 3

VCC = 4.5V
GND = -4.5V
V

EE

R

= 50Ω

L

PIN 12 TO 3

FIGURE 6. CHANNEL OFF FEEDTHROUGH (’HC4351,

CD74HCT4351)

0

-20

-40

dB

-60

-80

VCC = 2.25V
GND = -2.25V

= -2.25V

V

EE

= 50Ω

R

L

PIN 4 TO 3

VCC = 4.5V
GND = -4.5V
V

= -4.5V

EE

R

= 50Ω

L

PIN 4 TO 3

= -4.5V

-10
10K 100K 1M 10M 100M

FREQUENCY, f (Hz)

-100
10K 100K 1M 10M 100M

FREQUENCY, f (Hz)

FIGURE 7. CHANNEL ON BANDWIDTH (CD74HC4352) FIGURE 8. CHANNEL OFF FEEDTHROUGH (CD74HC4352)

11

CD54/74HC4351, CD74HCT4351, CD74HC4352

Typical Performance Curves

130
120
110

(Ω)

100

ON

90
80
70
60
50
40
30

“ON” RESISTANCE, R

20
10

0

FIGURE 9. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE

Analog Test Circuits

V

V

CC

IS

0.1µF

V

IS

SWITCH

R

ON

RC

/2

V

CC

(Continued)

VCC - VEE = 4.5V

VCC - VEE = 6V

VCC - VEE = 9V

123 456789

0

INPUT SIGNAL VOLTAGE, V

V

OS1

fIS = 1MHz SINEWAVE
R = 50Ω
C = 10pF

VCC/2

(V)

IS

V

R

SWITCH

OFF

CC

RC

/2

V

CC

V

OS2

dB

METER

FIGURE 10. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT

V

CC

SINE

0.1µF

V

IS

SWITCH

ON

50Ω 10pF

/2

V

CC

V

OS

dB

METER

10µF

WAVE

V

IS

fIS = 1kHz TO 10kHz

V

CC

SWITCH

ON

VI = V

10kΩ 50pF

/2

V

CC

V

IH

IS

V

OS

DISTORTION

METER

FIGURE 11. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 12. TOTAL HARMONIC DISTORTION TEST CIRCUIT

12

CD54/74HC4351, CD74HCT4351, CD74HC4352

Analog Test Circuits

V

CC

600Ω

/2

V

CC

SWITCH

ALTERNATING

ON AND OFF

t

, tf≤ 6ns

r

= 1MHz

f

CONT

50% DUTY

CYCLE

(Continued)

600Ω

V

/2

CC

E

V

50pF

OS

V

P-P

V

OS

SCOPE

FIGURE 13. CONTROL-TO-SWITCH FEEDTHROUGH NOISE

TEST CIRCUIT

V

CC

VC = V

0.1µF

V

IS

SWITCH

OFF

R

/2

V

CC

V

CC

fIS≥ 1MHz SINEWAVE
R = 50Ω

IL

C = 10pF

V

OS

RC

/2

dB

METER

FIGURE 14. SWITCH OFF SIGNAL FEEDTHROUGH

13

CD54/74HC4351, CD74HCT4351, CD74HC4352

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

fC

50%

1.3V

I

fC

L

3V

GND

+ tWH=

t

t

WL

WH

I

L

V

CC

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with devicetruth table. For f

, input duty cycle = 50%.

MAX

FIGURE 15. HC CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

TLH

CC

GND

INPUT

t

90%
50%
10%

THL

90%

t

50%

10%

PLH

INVERTING

OUTPUT

t

PHL

FIGURE 17. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tfC

L

V

CC

50%

GND

t

H(L)

V

CC

50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with devicetruth table. For f

, input duty cycle = 50%.

MAX

FIGURE 16. HCT CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 18. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

3V

1.3V
GND

t

H(L)

3V

1.3V

t

SU(L)

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 19. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V

SET, RESET

1.3V

90%

1.3V
t

t

PLH

TLH

90%

1.3V
10%

t

t

PHL

THL

OR PRESET

IC

C

L

50pF

FIGURE 20. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

14

GND

CD54/74HC4351, CD74HCT4351, CD74HC4352

Test Circuits and Waveforms

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS

ENABLED

PLZ

PHZ

90%

10%

90%

OUTPUTS

DISABLED

(Continued)

10%

t

PZL

t

PZH

50%

50%

FIGURE 21. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

IC WITH

THREE-

STATE

OUTPUT

V

CC

GND

OUTPUTS
ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

0.3

t

t

PZH

6ns

PZL

FIGURE 22. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

OUTPUT

R

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

3V

GND

1.3V

1.3V
OUTPUTS

ENABLED

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 23. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

PLZ

and t

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

PZL

15

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