Datasheet 74HC4094D.652 Specification

Page 1

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Rev. 6 — 31 December 2012 Product data sheet

1. General description

The 74HC4094; 74HCT4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the L OW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Dat a in the storage register appears at the outputs whenever th e output ena ble input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Ope ration of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V

2. Features and benefits

 Complies with JEDEC standard JESD7A  Input levels:

 For 74HC4094: CMOS level

 For 74HCT4094: TTL level  Low-power dissipation  ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V  Specifie d from 40 Cto+85C and from 40 Cto+125C

3. Applications

 Serial-to-parallel data conversion  Remote control holding register

Page 2

NXP Semiconductors

2OED

CP STR

QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7

QS1 QS2910

4 5

6 7 14 13 12 11

001aaf111

001aaf112

C1/

EN3

SRG8

5 6

7 14 13 12 11

9 10

32D

4. Ordering information

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC4094N 40 C to +125 C D IP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 74HCT4094N 74HC4094D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 74HCT4094D

3.9 mm

74HC4094DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; 74HCT4094DB

body width 5.3 mm

74HC4094PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;

SOT109-1

SOT338-1

SOT403-1

body width 4.4 mm

5. Functional diagram

Fig 1. Functional diagram Fig 2. Logic symbol

Product data sheet Rev. 6 — 31 December 2012 2 of 23

Page 3

NXP Semiconductors

001aaf119

8-STAGE SHIFT

8-BIT STORAGE

3-STATE OUTPUTS

QS2

QS1

QP0

4 5 6 7 14 13 12 11

QP1 QP2 QP3 QP4 QP5 QP6 QP7

STR

001aag799

FF 0

DLEQ

LATCH 0

DCPQ

FF 7

DLEQ

LATCH 7

STAGES 1 TO 6STAGE 0 STAGE 7

QP2

QP0

D QS2

QS1

LATCH

QP1

QP4

QP3

QP6

QP5

QP7

STR

Fig 3. Logic diagram

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 4. Logic diagram

Product data sheet Rev. 6 — 31 December 2012 3 of 23

Page 4

NXP Semiconductors

74HC4094

74HCT4094

STR V

DOE

CP QP4

QP0 QP5

QP1 QP6

QP2 QP7

QP3 QS2

GND QS1

001aan577

74HC4094

74HCT4094

STR V

DOE

CP QP4 QP0 QP5 QP1 QP6 QP2 QP7 QP3 QS2

GND QS1

001aan578

1 2 3 4 5 6 7 8

12 11

14 13

16 15

6. Pinning information

6.1 Pinning

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 5. Pin configuration DIP16 and SO16 Fig 6. Pin configuration SSOP16 and TSSOP16

6.2 Pin description

Table 2. Pin de scription

Symbol Pin Description

STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output V

QS1, QS2 9, 10 serial output OE 15 output enable input V

8 ground supply voltage

16 supply voltage

Product data sheet Rev. 6 — 31 December 2012 4 of 23

Page 5

NXP Semiconductors

001aaf117

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

OUTPUT QP0

INTERNAL Q6S (FF 6)

OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2

Z-state

74HC4094; 74HCT4094

8-stage shift-and-store bus register

7. Functional description

Table 3. Function table

Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2

 LXXZZQ6SNC  LXXZZNCQ7S  HLXNCNCQ6SNC  HHLLQPn 1Q6S NC  HHHHQPn 1Q6S NC  H H H NCNCNCQ7S

[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.

H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition; Z = HIGH-impedance OFF-state; NC = no change; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

[1]

Fig 7. Timing diagram

Product data sheet Rev. 6 — 31 December 2012 5 of 23

Page 6

NXP Semiconductors

8. Limiting values

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

GND

stg

tot

[1] For DIP16 package: P [2] For SO16: P

For SSOP16 and TSSOP16 packages: P

supply voltage 0.5 +7 V input clamping current VI < 0.5 V or VI>VCC+0.5 V - 20 mA output clamping current VO< 0.5 V or VO>VCC+0.5V - 20 mA output current VO = 0.5 V to (VCC+0.5V) - 25 mA supply current - +50 mA ground current - 50 mA storage temperature 65 +150 C total power dissipation DIP16 package

SO16, SSOP16 and TSSOP16 packages

derates linearly with 12 mW/K above 70 C.

tot

derates linearly with 8 mW/K above 70 C.

tot

derates linearly with 5.5 mW/K above 60 C.

tot

[1]

- 750 mW

[2]

- 500 mW

9. Recommended operating conditions

Table 5. Re commended operating conditions

Voltages are referenced to GND (ground = 0 V)

Symbol Parameter Conditions 74HC4094 74HCT4094 Unit

amb

supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - V output voltage 0 - V ambient temperature 40 +25 +125 40 +25 +125 C

t/V input transition rise and fall rate V

Min Typ Max Min Typ Max

0- VCCV

= 2.0 V - - 625 - - - ns/V

= 4.5 V - 1.67 139 - 1.67 139 ns/V

= 6.0 V--83---ns/V

Product data sheet Rev. 6 — 31 December 2012 6 of 23

Page 7

NXP Semiconductors

10. Static characteristics

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

74HC4094

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage

input leakage current

OFF-state output current

supply current VI=VCCor GND; IO=0A;

input

VCC= 2.0 V 1.5 1.2 - 1.5 - 1.5 - V

= 4.5 V 3.15 2.4 - 3.15 - 3.15 - V

= 6.0 V 4.2 3.2 - 4.2 - 4.2 - V

VCC= 2.0 V - 0.8 0.5 - 0.5 - 0.5 V

= 4.5 V - 2.1 1.35 - 1.35 - 1.35 V

= 6.0 V - 2.8 1.8 - 1.8 - 1.8 V

VI=VIHor V

IO= 20 A; VCC= 2.0 V 1.9 2.0 - 1.9 - 1.9 - V

= 20 A; VCC= 4.5 V 4.4 4.5 - 4.4 - 4.4 - V

= 20 A; VCC= 6.0 V 5.9 6.0 - 5.9 - 5.9 - V

= 4.0 mA; VCC= 4.5 V 3.98 4.32 - 3.84 - 3.7 - V

= 5.2 mA; VCC= 6.0 V 5.48 5.81 - 5.34 - 5.2 - V

VI=VIHor V

IO=20A; VCC= 2.0 V - 0 0.1 - 0.1 - 0.1 V I

=20A; VCC= 4.5 V - 0 0.1 - 0.1 - 0.1 V

=20A; VCC= 6.0 V - 0 0.1 - 0.1 - 0.1 V

= 4.0 mA; VCC= 4.5 V - 0.15 0.26 - 0.33 - 0.4 V

= 5.2 mA; VCC= 6.0 V - 0.16 0.26 - 0.33 - 0.4 V

VI=VCCor GND;

=6.0V

VI=VIHor VIL;

--0.1 - 1.0 - 1.0 A

--0.5 - 5.0 - 10.0 A

VO=VCCor GND;

=6.0V

- - 8.0 - 80 - 160 A

=6.0V

-3.5- pF

capacitance

74HCT4094

HIGH-level

VCC= 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V

input voltage

LOW-level

VCC= 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V

input voltage

HIGH-level output voltage

LOW-level output voltage

VI=VIHor VIL; VCC=4.5V

= 20 A 4.4 4.5 - 4.4 - 4.4 - V

= 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V

VI=VIHor VIL; VCC=4.5V

=20A - 0 0.1 - 0.1 - 0.1 V

= 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V

Product data sheet Rev. 6 — 31 December 2012 7 of 23

Page 8

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 6. Static characteristics

…continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions 25C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

input leakage current

OFF-state output current

VI=VCCor GND; VCC=5.5V

VI=VIHor VIL; VCC=5.5V; VO=VCCor GND per input pin; other inputs at V

--0.1 - 1.0 - 1.0 A

--0.5 - 5.0 - 10 A

GND; IO=0A

supply current VI=VCCor GND; IO=0A;

- - 8.0 - 80 - 160 A

VCC=5.5V

I

additional supply current

VI=VCC 2.1 V; other inputs at V

or GND;

VCC= 4.5 V to 5.5 V; IO=0A

per input pin; STR input - 100 360 - 450 - 490 A per input pin; OE input - 150 540 - 675 - 735 A per input pin; CP input - 150 540 - 675 - 735 A per input pin; D input - 40 144 - 180 - 196 A

input

-3.5- pF

capacitance

Product data sheet Rev. 6 — 31 December 2012 8 of 23

Page 9

NXP Semiconductors

11. Dynamic characteristics

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 7. Dynamic characteristics

Voltages are referenced to GND ( ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

74HC4094

propagation delay

CP to QS1; see Figure 8

VCC = 2.0 V - 50 150 - 190 - 225 ns

= 4.5 V - 18 30 - 38 - 45 ns

=5V; CL=15pF - 15 - - - - - ns

= 6.0 V - 14 26 - 33 - 38 ns

CP to QS2; see Figure 8

[1]

VCC = 2.0 V - 44 135 - 170 - 205 ns

= 4.5 V - 16 27 - 34 - 41 ns

=5V; CL=15pF - 13 - - - - - ns

= 6.0 V - 13 23 - 29 - 35 ns

CP to QPn; see Figure 8

[1]

VCC = 2.0 V - 63 195 - 245 - 295 ns

= 4.5 V - 23 39 - 49 - 59 ns

=5V; CL=15pF - 20 - - - - - ns

= 6.0 V - 18 33 - 42 - 50 ns

STR to QPn; see Figure 9

[1]

VCC = 2.0 V - 58 180 - 225 - 270 ns

= 4.5 V - 21 36 - 45 - 54 ns

=5V; CL=15pF - 18 - - - - - ns

= 6.0 V - 17 31 - 38 - 46 ns

enable time OE to QPn; see Figure 11

[2]

VCC = 2.0 V - 55 175 - 220 - 265 ns

= 4.5 V - 20 35 - 44 - 53 ns

= 6.0 V - 16 30 - 37 - 45 ns

dis

disable time OE to QPn; see Figure 11

[3]

VCC = 2.0 V - 41 125 - 155 - 190 ns

= 4.5 V - 15 25 - 31 - 38 ns

= 6.0 V - 12 21 - 26 - 32 ns

transition time

QPn and QSn; see

Figure 8

[4]

VCC = 2.0 V - 19 75 - 95 - 110 ns

= 4.5 V - 7 15 - 19 - 22 ns

= 6.0 V - 6 13 - 16 - 19 ns

Product data sheet Rev. 6 — 31 December 2012 9 of 23

Page 10

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 7. Dynamic characteristics …continued

Voltages are referenced to GND ( ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

max

pulse width CP HIGH or LOW;

see Figure 8

VCC = 2.0 V 80 14 - 100 - 120 - ns

= 4.5 V 16 5 - 20 - 24 - ns

= 6.0 V 14 4 - 17 - 20 - ns

STR HIGH; see Figure 9

VCC = 2.0 V 80 14 - 100 - 120 - ns

= 4.5 V 16 5 - 20 - 24 - ns

= 6.0 V 14 4 - 17 - 20 - ns

set-up time D to CP; see Figure 10

VCC = 2.0 V 50 14 - 65 - 75 - ns

= 4.5 V 10 5 - 13 - 15 - ns

= 6.0 V 9 4 - 11 - 13 - ns

CP to STR; see Figure 9

VCC = 2.0 V 100 28 - 125 - 150 - ns

= 4.5 V 20 10 - 25 - 30 - ns

= 6.0 V 17 8 - 21 - 26 - ns

hold time D to CP; see Figure 10

VCC = 2.0 V 3 -6 - 3 - 3 - ns

= 4.5 V 3 -2 - 3 - 3 - ns

= 6.0 V 3 -2 - 3 - 3 - ns

CP to STR; see Figure 9

VCC = 2.0 V 0 -14 - 0 - 0 - ns

= 4.5 V 0 -5 - 0 - 0 - ns

= 6.0 V 0 -4 - 0 - 0 - ns

maximum frequency

power dissipation

CP; see Figure 8

VCC = 2.0 V 6.0 28 - 4.8 - 4.0 - MHz

= 4.5 V 30 87 - 24 - 20 - MHz

=5V; CL=15pF - 95 - - - - - MHz

= 6.0 V 35 103 - 28 - 24 - MHz

CL= 50 pF; f = 1 MHz;

=GNDtoV

capacitance

[5]

-83- - - - -pF

Product data sheet Rev. 6 — 31 December 2012 10 of 23

Page 11

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 7. Dynamic characteristics …continued

Voltages are referenced to GND ( ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12.

Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit

Min Typ Max Min Max Min Max

74HCT4094

dis

max

propagation delay

CP to QS1; see Figure 8

VCC = 4.5 V - 23 39 - 49 - 59 ns

=5V; CL=15pF - 19 - - - - - ns

CP to QS2; see Figure 8

VCC = 4.5 V - 21 36 - 45 - 54 ns

=5V; CL=15pF - 18 - - - - - ns

CP to QPn; see Figure 8

VCC = 4.5 V - 25 43 - 54 - 65 ns

=5V; CL=15pF - 21 - - - - - ns

STR to QPn; see Figure 9

VCC = 4.5 V - 22 39 - 49 - 59 ns

=5V; CL=15pF - 19 - - - - - ns

enable time OE to QPn; see Figure 11

VCC = 4.5 V - 20 35 - 44 - 53 ns

disable time OE to QPn; see Figure 11

VCC = 4.5 V - 21 35 - 44 - 53 ns

transition time

QPn and QSn; see

Figure 8

VCC = 4.5 V - 7 15 - 19 - 22 ns

pulse width CP HIGH or LOW;

see Figure 8

VCC = 4.5 V 16 7 - 20 - 24 - ns

STR HIGH; see Figure 9

VCC = 4.5 V 16 5 - 20 - 24 - ns

set-up time Dn to CP; see Figure 10

VCC = 4.5 V 10 4 - 13 - 15 - ns

CP to STR; see Figure 9

VCC = 4.5 V 20 9 - 25 - 30 - ns

hold time Dn to CP; see Figure 10

VCC = 4.5 V 4 0 - 4 - 4 - ns

CP to STR; see Figure 9

VCC = 4.5 V 0 4- 0 - 0 - ns

maximum frequency

power dissipation

CP; see Figure 8

VCC = 4.5 V 30 80 - 24 - 20 - MHz

=5V; CL=15pF - 86 - - - - - MHz

CL= 50 pF; f = 1 MHz; VI=GNDtoV

capacitance

[1]

[2]

[3]

[4]

[5]

-92- - - - -pF

[1] tpd is the same as t

Product data sheet Rev. 6 — 31 December 2012 11 of 23

PLH

and t

PHL

Page 12

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

[2] ten is the same as t [3] t

is the same as t

dis

is the same as t

[4] t

[5] C

is used to determine the dynamic power dissipation (PD in W).

= input frequency in MHz;

C V

 V

D=CPD

= output frequency in MHz;

= output load capacitance in pF;

= supply voltage in V;

PZH

PLZ

and t

THL

 fi N+(CL V

N = number of inputs switching;

 V

(C

 fo) = sum of outputs.

12. Waveforms

and t

PZL

and t

PHZ

TLH

QPn, QS1 output

CP input

QS2 output

 fo) where:

GND

TLH

PLH

1/f

max

PHL

PLH

90 %

10 %

THL

PHL

aaa-003132

Measurement points are given in Table 8.

and VOH are typical voltage output levels that occur with the output load.

Fig 8. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse

width and the maximum frequency (CP)

Product data sheet Rev. 6 — 31 December 2012 12 of 23

Page 13

NXP Semiconductors

PHL

PLH

GND

QPn output

STR input

001aaf114

GND

CP input

001aaf115

GND

QPn, QS1, QS2 output

CP input

D input

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Measurement points are given in Table 8. V

and VOH are typical voltage output levels that occur with the output load.

Fig 9. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock

set-up and hold times for strobe input

Fig 10. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times

Product data sheet Rev. 6 — 31 December 2012 13 of 23

Measurement points are given in Table 8.

and VOH are typical voltage output levels that occur with the output load.

Page 14

NXP Semiconductors

001aaf116

PLZ

PHZ

outputs

disabled

outputs enabled

outputs

enabled

output LOW-to-OFF OFF-to-LOW

output

HIGH-to-OFF OFF-to-HIGH

OE input

GND

PZL

PZH

GND

Measurement points are given in Table 8.

and VOH are typical voltage output levels that occur with the output load.

Fig 11. Enable and disable times

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Table 8. Measur ement points

Type Input Output

74HC4094 0.5V

74HCT4094 1.3 V 1.3 V 0.1V

Product data sheet Rev. 6 — 31 December 2012 14 of 23

0.5V

0.1V

OH OH

0.9V

OH OH

Page 15

NXP Semiconductors

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

90 %

10 %

001aad983

DUT

RLS1

open

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 12. Test circuit for measuring switching times

Table 9. Test data

Type Input Load S1 position

74HC4094 V 74HCT4094 3 V 6 ns 15 pF, 50 pF 1 k open GND V

Test data is given in Table 9. Definitions test circuit:

= Termination resistance should be equal to output impedance Zo of the pulse generator.

= Load capacitance including jig and probe capacitance.

= Load resistance.

S1 = Test selection switch.

tr, t

6ns 15pF, 50 pF 1k open GND V

PHL

, t

PLH

PZH

, t

PHZ

PZL

CC CC

, t

PLZ

Product data sheet Rev. 6 — 31 December 2012 15 of 23

Page 16

NXP Semiconductors

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

SOT38-4

95-01-14 03-02-13

(e )

seating plane

w M

pin 1 index

0 5 10 mm

scale

Note

1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

UNIT

max.

(1) (1)

(1)

cD E e M

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

min.

max.

1.73

1.30

0.53

0.38

0.36

0.23

19.50

18.55

6.48

6.20

3.60

3.05

0.2542.54 7.62

8.25

7.80

10.0

8.3

0.764.2 0.51 3.2

inches

0.068

0.051

0.021

0.015

0.014

0.009

1.25

0.85

0.049

0.033

0.77

0.73

0.26

0.24

0.14

0.12

0.010.1 0.3

0.32

0.31

0.39

0.33

0.030.17 0.02 0.13

DIP16: plastic dual in-line package; 16 leads (300 mil)

SOT38-4

13. Package outline

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 13. Package outline SOT38-4 (DIP16)

Product data sheet Rev. 6 — 31 December 2012 16 of 23

Page 17

NXP Semiconductors

w M

detail X

v M

(A )

pin 1 index

UNIT

max.

A2A3b

(1)E(1) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

inches

1.75

0.25

0.10

1.45

1.25

0.25

0.49

0.36

0.25

0.19

10.0

9.8

4.0

3.8

1.27

6.2

5.8

0.7

0.6

0.7

0.3

8 0

o o

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT109-1

99-12-27 03-02-19

076E07 MS-012

0.069

0.010

0.004

0.057

0.049

0.01

0.019

0.014

0.0100

0.0075

0.39

0.38

0.16

0.15

0.05

1.05

0.041

0.244

0.228

0.028

0.020

0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

0 2.5 5 mm

scale

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 14. Package outline SOT109-1 (SO16)

Product data sheet Rev. 6 — 31 December 2012 17 of 23

Page 18

NXP Semiconductors

UNIT A1A2A3b

(1)E(1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.21

0.05

1.80

1.65

0.25

0.38

0.25

0.20

0.09

6.4

6.0

5.4

5.2

0.65 1.25

7.9

7.6

1.03

0.63

0.9

0.7

1.00

0.55

8 0

o o

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT338-1

99-12-27 03-02-19

(1)

w M

v M

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

max.

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 15. Package outline SOT338-1 (SSOP16)

Product data sheet Rev. 6 — 31 December 2012 18 of 23

Page 19

NXP Semiconductors

UNIT A1A2A

(1)E(2) (1)

eHELLpQZywv θ

REFERENCES

OUTLINE VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC JEITA

0.15

0.05

0.95

0.80

0.30

0.19

0.2

0.1

5.1

4.9

4.5

4.3

0.65

6.6

6.2

0.4

0.3

0.40

0.06

8 0

o o

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT403-1 MO-153

99-12-27 03-02-18

w M

0.25

detail X

(A )

v M

0 2.5 5 mm

scale

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

max.

1.1

pin 1 index

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Fig 16. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 6 — 31 December 2012 19 of 23

Page 20

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

14. Abbreviations

Table 10. Abbreviations

Acronym Description

CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model

15. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74HC_HCT4094 v.6 20121231 Product data sheet - 74HC_HCT4094 v.5 Modifications: 74HC_HCT4094 v.5 20120628 Product data sheet - 74HC_HCT4094 v.4 Modifications: 74HC_HCT4094 v.4 20111219 Product data sheet - 74HC_HCT4094 v.3 Modifications: 74HC_HCT4094 v.3 20110214 Product data sheet - 74HC_HCT4094_CNV v.2 74HC_HCT4094_CNV v.2 19970901 Product specification - -

• General description updated.

• V

and VY measurement points added to Table 8.

• Legal pages updated.

Product data sheet Rev. 6 — 31 December 2012 20 of 23

Page 21

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

16. Legal information

16.1 Data sheet status

Document status

Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) d escribed i n this docu ment may have changed si nce this d ocument was p ublished and may dif fer in case of multiple devices. The latest product statu s

information is available on the Internet at URL http://www.nxp.com.

[1][2]

Product status

[3]

Definition

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to co nt ain det ailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.

16.3 Disclaimers

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semi conductors’ aggregat e and cumulative liabil ity towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the cust omer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default , damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third part y customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell product s that is open for accept ance or the gr ant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

, unless otherwise

Product data sheet Rev. 6 — 31 December 2012 21 of 23

Page 22

NXP Semiconductors

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It i s neit her qua lif ied nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, custome r (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, da mages or failed produ ct claims result ing from custome r design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (t ranslated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

16.4 Trademarks

Notice: All referenced brands, prod uct names, service names and trademarks are the property of their respective owners.

17. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Product data sheet Rev. 6 — 31 December 2012 22 of 23

Page 23

NXP Semiconductors

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4

7 Functional description . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 20

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 20

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 21

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22

17 Contact information. . . . . . . . . . . . . . . . . . . . . 22

18 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

74HC4094; 74HCT4094

8-stage shift-and-store bus register

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 31 December 2012

Document identifier: 74HC_HCT4094