Datasheet 74HCT4040U, 74HCT4040PW, 74HCT4040N, 74HCT4040D, 74HC4040U Datasheet (Philips)
...Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT4040
12-stage binary ripple counter
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
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December 1990 2
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
FEATURES
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4040 are high-speed Si-gate CMOS
devices and are pin compatible with “4040” of the “4000B”
series. They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT4040 are 12-stage binary ripple counters
with a clock input (
CP), an overriding asynchronous
master reset input (MR) and twelve parallel outputs
(Q0 to Q11). The counter advances on the HIGH-to-LOW
transition of CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
APPLICATIONS
• Frequency dividing circuits
• Time delay circuits
• Control counters
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC=5 V
CP to Q
0
14 16 ns
Q
n
to Q
n+1
88ns
f
max
maximum clock frequency 90 79 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 20 20 pF
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December 1990 3
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
8 GND ground (0 V)
9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1 Q
0
to Q
11
parallel outputs
10
CP clock input (HIGH-to-LOW, edge-triggered)
11 MR master reset input (active HIGH)
16 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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December 1990 4
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
Fig.4 Functional diagram.
Fig.5 Logic diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock
transition
↓ = HIGH-to-LOW clock
transition
INPUTS OUTPUTS
CP MR Q
n
↑
↓
X
L
L
H
no change
count
L
Fig.6 Timing diagram.
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December 1990 5
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
Qn to Q
n+1
28
10
8
100
20
17
125
25
21
150
30
26
ns 2.0
4.5
6.0
Fig.7
t
PHL
propagation delay
MR to Q
n
61
22
18
185
37
31
230
46
39
280
56
48
ns 2.0
4.5
6.0
Fig.7
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Fig.7
t
W
clock pulse width
HIGH or LOW
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
W
master reset pulse
width; HIGH
80
16
14
22
8
6
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
rem
removal time
MR to CP
50
10
9
8
3
2
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.7
f
max
maximum clock pulse
frequency
6.0
30
35
27
82
98
4.8
24
28
4.0
20
24
MHz 2.0
4.5
6.0
Fig.7
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December 1990 6
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆I
CC
per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
CP
MR
0.85
1.10
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
19 40 50 60 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
Qn to Q
n+1
10 20 25 30 ns 4.5 Fig.7
t
PHL
propagation delay
MR to Q
n
23 45 56 68 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.7
t
W
clock pulse width
HIGH or LOW
16 7 20 24 ns 4.5 Fig.7
t
W
master reset pulse
width; HIGH
16 6 20 24 ns 4.5 Fig.7
t
rem
removal time
MR to CP
10 2 13 15 ns 4.5 Fig.7
f
max
maximum clock pulse
frequency
30 72 24 20 MHz 4.5 Fig.7
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December 1990 7
Philips Semiconductors Product specification
12-stage binary ripple counter 74HC/HCT4040
AC WAVEFORMS
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock pulse frequency.
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and
the master reset to clock (CP) removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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